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hw/arm/exynos4210: Use TYPE_OR_IRQ instead of custom OR-gate device 

The Exynos4210 SoC device currently uses a custom device
"exynos4210.irq_gate" to model the OR gate that feeds each CPU's IRQ
line.  We have a standard TYPE_OR_IRQ device for this now, so use
that instead.

(This is a migration compatibility break, but that is OK for this
machine type.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-2-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2022-04-04 16:46:41 +01:00
parent d6ccfc7e67
commit 2bd84b6818
2 changed files with 17 additions and 15 deletions
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29
hw/arm/exynos4210.c
View File

@ -205,7 +205,6 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
{ {
Exynos4210State *s = EXYNOS4210_SOC(socdev); Exynos4210State *s = EXYNOS4210_SOC(socdev);
MemoryRegion *system_mem = get_system_memory(); MemoryRegion *system_mem = get_system_memory();
qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
SysBusDevice *busdev; SysBusDevice *busdev;
DeviceState *dev, *uart[4], *pl330[3]; DeviceState *dev, *uart[4], *pl330[3];
int i, n; int i, n;
@ -235,17 +234,12 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
/* IRQ Gate */ /* IRQ Gate */
for (i = 0; i < EXYNOS4210_NCPUS; i++) { for (i = 0; i < EXYNOS4210_NCPUS; i++) {
dev = qdev_new("exynos4210.irq_gate"); DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]);
qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS); object_property_set_int(OBJECT(orgate), "num-lines",
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); EXYNOS4210_IRQ_GATE_NINPUTS,
/* Get IRQ Gate input in gate_irq */ &error_abort);
for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) { qdev_realize(orgate, NULL, &error_abort);
gate_irq[i][n] = qdev_get_gpio_in(dev, n); qdev_connect_gpio_out(orgate, 0,
}
busdev = SYS_BUS_DEVICE(dev);
/* Connect IRQ Gate output to CPU's IRQ line */
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ)); qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ));
} }
@ -256,7 +250,8 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
sysbus_realize_and_unref(busdev, &error_fatal); sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
for (n = 0; n < EXYNOS4210_NCPUS; n++) { for (n = 0; n < EXYNOS4210_NCPUS; n++) {
sysbus_connect_irq(busdev, n, gate_irq[n][0]); sysbus_connect_irq(busdev, n,
qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0));
} }
for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n); s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
@ -275,7 +270,8 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
/* Map Distributer interface */ /* Map Distributer interface */
sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR); sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
for (n = 0; n < EXYNOS4210_NCPUS; n++) { for (n = 0; n < EXYNOS4210_NCPUS; n++) {
sysbus_connect_irq(busdev, n, gate_irq[n][1]); sysbus_connect_irq(busdev, n,
qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1));
} }
for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n); s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
@ -488,6 +484,11 @@ static void exynos4210_init(Object *obj)
object_initialize_child(obj, name, orgate, TYPE_OR_IRQ); object_initialize_child(obj, name, orgate, TYPE_OR_IRQ);
g_free(name); g_free(name);
} }
for (i = 0; i < ARRAY_SIZE(s->cpu_irq_orgate); i++) {
g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i);
object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ);
}
} }
static void exynos4210_class_init(ObjectClass *klass, void *data) static void exynos4210_class_init(ObjectClass *klass, void *data)

1
include/hw/arm/exynos4210.h
View File

@ -102,6 +102,7 @@ struct Exynos4210State {
MemoryRegion bootreg_mem; MemoryRegion bootreg_mem;
I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA]; qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
}; };
#define TYPE_EXYNOS4210_SOC "exynos4210" #define TYPE_EXYNOS4210_SOC "exynos4210"