From 2b9e0a6b9456dcb4b9e2f14d90a9db1622f462ba Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 15 Feb 2019 18:00:20 +0100 Subject: [PATCH] target/ppc: Re-enable RMLS on POWER9 for virtual hypervisors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Historically the 64-bit server MMU supports two way of configuring the guest "real mode" mapping: - The "RMA" with is a single chunk of physically contiguous memory remapped as guest real, and controlled by the RMLS field in the LPCR register and the RMOR register. - The "VRMA" which uses special PTEs inserted in the partition hash table by the hypervisor. POWER9 deprecates the former, which is reflected by the filtering done in ppc_store_lpcr() which effectively prevents setting of the RMLS field. However, when using fully emulated SPAPR machines, our qemu code currently only knows how to define the guest real mode memory using RMLS. Thus you cannot run a SPAPR machine anymore with a POWER9 CPU model today. This works around it with a quirk in ppc_store_lpcr() to continue allowing the RMLS field to be set when using a virtual hypervisor. Ultimately we will want to implement configuring a VRMA instead which will also be necessary if we want to migrate a SPAPR guest between TCG and KVM but this is a lot more work. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Cédric Le Goater Message-Id: <20190215170029.15641-4-clg@kaod.org> Signed-off-by: David Gibson --- target/ppc/mmu-hash64.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index f1c7729332..1175b991d9 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -1088,6 +1088,14 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC | LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE); + /* + * If we have a virtual hypervisor, we need to bring back RMLS. It + * doesn't exist on an actual P9 but that's all we know how to + * configure with softmmu at the moment + */ + if (cpu->vhyp) { + lpcr |= (val & LPCR_RMLS); + } break; default: ;