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target-i386: Update X86CPU to QOM realizefn 

Adapt the signature of x86_cpu_realize(), hook up to
DeviceClass::realize and set realized = true in cpu_x86_init().

The QOM realizefn cannot depend on errp being non-NULL as in
cpu_x86_init(), so use a local Error to preserve error handling behavior
on APIC initialization errors.

Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
[AF: Invoke parent's realizefn]
Signed-off-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Andreas Färber 2013-01-16 03:41:47 +01:00
parent 149692667f
commit 2b6f294cac
3 changed files with 18 additions and 8 deletions
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5
target-i386/cpu-qom.h
View File

@ -39,6 +39,7 @@
/** /**
* X86CPUClass: * X86CPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler. * @parent_reset: The parent class' reset handler.
* *
* An x86 CPU model or family. * An x86 CPU model or family.
@ -48,6 +49,7 @@ typedef struct X86CPUClass {
CPUClass parent_class; CPUClass parent_class;
/*< public >*/ /*< public >*/
DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu); void (*parent_reset)(CPUState *cpu);
} X86CPUClass; } X86CPUClass;
@ -72,8 +74,5 @@ static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
#define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e)) #define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e))
/* TODO Drop once ObjectClass::realize is available */
void x86_cpu_realize(Object *obj, Error **errp);
#endif #endif

19
target-i386/cpu.c
View File

@ -2060,10 +2060,14 @@ static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
} }
#endif #endif
void x86_cpu_realize(Object *obj, Error **errp) static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
{ {
X86CPU *cpu = X86_CPU(obj); X86CPU *cpu = X86_CPU(dev);
X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
CPUX86State *env = &cpu->env; CPUX86State *env = &cpu->env;
#ifndef CONFIG_USER_ONLY
Error *local_err = NULL;
#endif
if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) { if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
env->cpuid_level = 7; env->cpuid_level = 7;
@ -2105,8 +2109,9 @@ void x86_cpu_realize(Object *obj, Error **errp)
qemu_register_reset(x86_cpu_machine_reset_cb, cpu); qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) { if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
x86_cpu_apic_init(cpu, errp); x86_cpu_apic_init(cpu, &local_err);
if (error_is_set(errp)) { if (local_err != NULL) {
error_propagate(errp, local_err);
return; return;
} }
} }
@ -2115,6 +2120,8 @@ void x86_cpu_realize(Object *obj, Error **errp)
mce_init(cpu); mce_init(cpu);
qemu_init_vcpu(&cpu->env); qemu_init_vcpu(&cpu->env);
cpu_reset(CPU(cpu)); cpu_reset(CPU(cpu));
xcc->parent_realize(dev, errp);
} }
/* Enables contiguous-apic-ID mode, for compatibility */ /* Enables contiguous-apic-ID mode, for compatibility */
@ -2200,6 +2207,10 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
{ {
X86CPUClass *xcc = X86_CPU_CLASS(oc); X86CPUClass *xcc = X86_CPU_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc); CPUClass *cc = CPU_CLASS(oc);
DeviceClass *dc = DEVICE_CLASS(oc);
xcc->parent_realize = dc->realize;
dc->realize = x86_cpu_realizefn;
xcc->parent_reset = cc->reset; xcc->parent_reset = cc->reset;
cc->reset = x86_cpu_reset; cc->reset = x86_cpu_reset;

2
target-i386/helper.c
View File

@ -1282,7 +1282,7 @@ X86CPU *cpu_x86_init(const char *cpu_model)
return NULL; return NULL;
} }
x86_cpu_realize(OBJECT(cpu), &error); object_property_set_bool(OBJECT(cpu), true, "realized", &error);
if (error) { if (error) {
error_free(error); error_free(error);
object_unref(OBJECT(cpu)); object_unref(OBJECT(cpu));