ShuriZma
/
xemu
mirror of https://github.com/xemu-project/xemu.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

target/openrisc: Implement unordered fp comparisons 

These were added to the 1.3 spec.  For OF32S, validate AVR.
But OF64A32 is itself new to 1.3 so no extra check needed.

Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2019-05-14 06:39:47 -07:00
parent 62f2b0389f
commit 2b13b4b93d
5 changed files with 145 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
target/openrisc/disas.c
View File

@ -166,6 +166,12 @@ FP_INSN(sfgt, s, "r%d, r%d", a->a, a->b)
FP_INSN(sfge, s, "r%d, r%d", a->a, a->b)
FP_INSN(sflt, s, "r%d, r%d", a->a, a->b)
FP_INSN(sfle, s, "r%d, r%d", a->a, a->b)
FP_INSN(sfun, s, "r%d, r%d", a->a, a->b)
FP_INSN(sfueq, s, "r%d, r%d", a->a, a->b)
FP_INSN(sfuge, s, "r%d, r%d", a->a, a->b)
FP_INSN(sfugt, s, "r%d, r%d", a->a, a->b)
FP_INSN(sfule, s, "r%d, r%d", a->a, a->b)
FP_INSN(sfult, s, "r%d, r%d", a->a, a->b)
FP_INSN(add, d, "r%d,r%d, r%d,r%d, r%d,r%d",
a->d, a->d + a->dp + 1,
@ -222,3 +228,21 @@ FP_INSN(sflt, d, "r%d,r%d, r%d,r%d",
FP_INSN(sfle, d, "r%d,r%d, r%d,r%d",
a->a, a->a + a->ap + 1,
a->b, a->b + a->bp + 1)
FP_INSN(sfun, d, "r%d,r%d, r%d,r%d",
a->a, a->a + a->ap + 1,
a->b, a->b + a->bp + 1)
FP_INSN(sfueq, d, "r%d,r%d, r%d,r%d",
a->a, a->a + a->ap + 1,
a->b, a->b + a->bp + 1)
FP_INSN(sfuge, d, "r%d,r%d, r%d,r%d",
a->a, a->a + a->ap + 1,
a->b, a->b + a->bp + 1)
FP_INSN(sfugt, d, "r%d,r%d, r%d,r%d",
a->a, a->a + a->ap + 1,
a->b, a->b + a->bp + 1)
FP_INSN(sfule, d, "r%d,r%d, r%d,r%d",
a->a, a->a + a->ap + 1,
a->b, a->b + a->bp + 1)
FP_INSN(sfult, d, "r%d,r%d, r%d,r%d",
a->a, a->a + a->ap + 1,
a->b, a->b + a->bp + 1)

20
target/openrisc/fpu_helper.c
View File

@ -135,4 +135,24 @@ target_ulong helper_float_ ## name ## _s(CPUOpenRISCState *env, \
FLOAT_CMP(le, le)
FLOAT_CMP(lt, lt)
FLOAT_CMP(eq, eq_quiet)
FLOAT_CMP(un, unordered_quiet)
#undef FLOAT_CMP
#define FLOAT_UCMP(name, expr) \
target_ulong helper_float_ ## name ## _d(CPUOpenRISCState *env, \
uint64_t fdt0, uint64_t fdt1) \
{ \
int r = float64_compare_quiet(fdt0, fdt1, &env->fp_status); \
return expr; \
} \
target_ulong helper_float_ ## name ## _s(CPUOpenRISCState *env, \
uint32_t fdt0, uint32_t fdt1) \
{ \
int r = float32_compare_quiet(fdt0, fdt1, &env->fp_status); \
return expr; \
}
FLOAT_UCMP(ueq, r == float_relation_equal || r == float_relation_unordered)
FLOAT_UCMP(ult, r == float_relation_less || r == float_relation_unordered)
FLOAT_UCMP(ule, r != float_relation_greater)
#undef FLOAT_UCMP

4
target/openrisc/helper.h
View File

@ -52,6 +52,10 @@ DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_RWG, tl, env, i64, i64)
FOP_CMP(eq)
FOP_CMP(lt)
FOP_CMP(le)
FOP_CMP(un)
FOP_CMP(ueq)
FOP_CMP(ule)
FOP_CMP(ult)
#undef FOP_CMP
/* interrupt */

12
target/openrisc/insns.decode
View File

@ -190,6 +190,12 @@ lf_sfgt_s 110010 ----- a:5 b:5 --- 00001010
lf_sfge_s 110010 ----- a:5 b:5 --- 00001011
lf_sflt_s 110010 ----- a:5 b:5 --- 00001100
lf_sfle_s 110010 ----- a:5 b:5 --- 00001101
lf_sfueq_s 110010 ----- a:5 b:5 --- 00101000
lf_sfuge_s 110010 ----- a:5 b:5 --- 00101011
lf_sfugt_s 110010 ----- a:5 b:5 --- 00101010
lf_sfule_s 110010 ----- a:5 b:5 --- 00101101
lf_sfult_s 110010 ----- a:5 b:5 --- 00101100
lf_sfun_s 110010 ----- a:5 b:5 --- 00101110
####
# DP Instructions
@ -218,3 +224,9 @@ lf_sfgt_d 110010 00000 ..... ..... 0.. 00011010 @ab_pair
lf_sfge_d 110010 00000 ..... ..... 0.. 00011011 @ab_pair
lf_sflt_d 110010 00000 ..... ..... 0.. 00011100 @ab_pair
lf_sfle_d 110010 00000 ..... ..... 0.. 00011101 @ab_pair
lf_sfueq_d 110010 00000 ..... ..... 0.. 00111000 @ab_pair
lf_sfuge_d 110010 00000 ..... ..... 0.. 00111011 @ab_pair
lf_sfugt_d 110010 00000 ..... ..... 0.. 00111010 @ab_pair
lf_sfule_d 110010 00000 ..... ..... 0.. 00111101 @ab_pair
lf_sfult_d 110010 00000 ..... ..... 0.. 00111100 @ab_pair
lf_sfun_d 110010 00000 ..... ..... 0.. 00111110 @ab_pair

85
target/openrisc/translate.c
View File

@ -46,6 +46,7 @@ typedef struct DisasContext {
uint32_t tb_flags;
uint32_t delayed_branch;
uint32_t cpucfgr;
uint32_t avr;
/* If not -1, jmp_pc contains this value and so is a direct jump. */
target_ulong jmp_pc_imm;
@ -141,6 +142,11 @@ static void gen_illegal_exception(DisasContext *dc)
dc->base.is_jmp = DISAS_NORETURN;
}
static bool check_v1_3(DisasContext *dc)
{
return dc->avr >= 0x01030000;
}
static bool check_of32s(DisasContext *dc)
{
return dc->cpucfgr & CPUCFGR_OF32S;
@ -1265,6 +1271,54 @@ static bool trans_lf_sfle_s(DisasContext *dc, arg_ab *a)
return do_fpcmp(dc, a, gen_helper_float_le_s, false, false);
}
static bool trans_lf_sfueq_s(DisasContext *dc, arg_ab *a)
{
if (!check_v1_3(dc)) {
return false;
}
return do_fpcmp(dc, a, gen_helper_float_ueq_s, false, false);
}
static bool trans_lf_sfult_s(DisasContext *dc, arg_ab *a)
{
if (!check_v1_3(dc)) {
return false;
}
return do_fpcmp(dc, a, gen_helper_float_ult_s, false, false);
}
static bool trans_lf_sfugt_s(DisasContext *dc, arg_ab *a)
{
if (!check_v1_3(dc)) {
return false;
}
return do_fpcmp(dc, a, gen_helper_float_ult_s, false, true);
}
static bool trans_lf_sfule_s(DisasContext *dc, arg_ab *a)
{
if (!check_v1_3(dc)) {
return false;
}
return do_fpcmp(dc, a, gen_helper_float_ule_s, false, false);
}
static bool trans_lf_sfuge_s(DisasContext *dc, arg_ab *a)
{
if (!check_v1_3(dc)) {
return false;
}
return do_fpcmp(dc, a, gen_helper_float_ule_s, false, true);
}
static bool trans_lf_sfun_s(DisasContext *dc, arg_ab *a)
{
if (!check_v1_3(dc)) {
return false;
}
return do_fpcmp(dc, a, gen_helper_float_un_s, false, false);
}
static bool check_pair(DisasContext *dc, int r, int p)
{
return r + 1 + p < 32;
@ -1490,6 +1544,36 @@ static bool trans_lf_sfle_d(DisasContext *dc, arg_ab_pair *a)
return do_dpcmp(dc, a, gen_helper_float_le_d, false, false);
}
static bool trans_lf_sfueq_d(DisasContext *dc, arg_ab_pair *a)
{
return do_dpcmp(dc, a, gen_helper_float_ueq_d, false, false);
}
static bool trans_lf_sfule_d(DisasContext *dc, arg_ab_pair *a)
{
return do_dpcmp(dc, a, gen_helper_float_ule_d, false, false);
}
static bool trans_lf_sfuge_d(DisasContext *dc, arg_ab_pair *a)
{
return do_dpcmp(dc, a, gen_helper_float_ule_d, false, true);
}
static bool trans_lf_sfult_d(DisasContext *dc, arg_ab_pair *a)
{
return do_dpcmp(dc, a, gen_helper_float_ult_d, false, false);
}
static bool trans_lf_sfugt_d(DisasContext *dc, arg_ab_pair *a)
{
return do_dpcmp(dc, a, gen_helper_float_ult_d, false, true);
}
static bool trans_lf_sfun_d(DisasContext *dc, arg_ab_pair *a)
{
return do_dpcmp(dc, a, gen_helper_float_un_d, false, false);
}
static void openrisc_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs)
{
DisasContext *dc = container_of(dcb, DisasContext, base);
@ -1500,6 +1584,7 @@ static void openrisc_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs)
dc->tb_flags = dc->base.tb->flags;
dc->delayed_branch = (dc->tb_flags & TB_FLAGS_DFLAG) != 0;
dc->cpucfgr = env->cpucfgr;
dc->avr = env->avr;
dc->jmp_pc_imm = -1;
bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;