mirror of https://github.com/xemu-project/xemu.git
nvnet: Start using tracing infrastructure for logging
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d40a1c578d
commit
2b05f7d50b
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@ -19,6 +19,7 @@
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*/
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#include "qemu/osdep.h"
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#include "trace.h"
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#include "hw/hw.h"
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#include "hw/i386/pc.h"
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#include "hw/pci/pci.h"
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@ -362,9 +363,9 @@ static ssize_t nvnet_receive_iov(NetClientState *nc,
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/* Utility Functions */
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static void nvnet_hex_dump(NvNetState *s, const uint8_t *buf, int size);
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#ifdef DEBUG
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static const char *nvnet_get_reg_name(hwaddr addr);
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static const char *nvnet_get_mii_reg_name(uint8_t reg);
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#ifdef DEBUG
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static void nvnet_dump_ring_descriptors(NvNetState *s);
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#endif
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@ -465,15 +466,13 @@ static int nvnet_mii_rw(NvNetState *s, uint64_t val)
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reg = mii_ctl & ((1 << NVREG_MIICTL_ADDRSHIFT) - 1);
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write = mii_ctl & NVREG_MIICTL_WRITE;
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NVNET_DPRINTF("nvnet mii %s: phy 0x%x %s [0x%x]\n",
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write ? "write" : "read", phy_addr, nvnet_get_mii_reg_name(reg), reg);
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if (phy_addr != 1) {
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return -1;
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retval = -1;
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goto out;
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}
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if (write) {
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return retval;
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goto out;
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}
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switch (reg) {
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@ -495,6 +494,13 @@ static int nvnet_mii_rw(NvNetState *s, uint64_t val)
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break;
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}
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out:
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if (write) {
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trace_nvnet_mii_write(phy_addr, reg, nvnet_get_mii_reg_name(reg), val);
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} else {
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trace_nvnet_mii_read(phy_addr, reg, nvnet_get_mii_reg_name(reg),
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retval);
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}
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return retval;
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}
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@ -532,9 +538,7 @@ static uint64_t nvnet_mmio_read(void *opaque, hwaddr addr, unsigned int size)
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break;
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}
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NVNET_DPRINTF("nvnet mmio: read %s [0x%llx] <- 0x%llx\n",
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nvnet_get_reg_name(addr & ~3), addr, retval);
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trace_nvnet_reg_read(addr, nvnet_get_reg_name(addr & ~3), size, retval);
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return retval;
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}
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@ -544,13 +548,10 @@ static uint64_t nvnet_mmio_read(void *opaque, hwaddr addr, unsigned int size)
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static void nvnet_mmio_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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NvNetState *s;
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NvNetState *s = NVNET_DEVICE(opaque);
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uint32_t temp;
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s = NVNET_DEVICE(opaque);
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NVNET_DPRINTF("nvnet mmio: write %s [0x%llx] = 0x%llx\n",
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nvnet_get_reg_name(addr & ~3), addr, val);
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trace_nvnet_reg_write(addr, nvnet_get_reg_name(addr & ~3), size, val);
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switch (addr) {
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case NvRegRingSizes:
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@ -849,14 +850,15 @@ static void nvnet_set_link_status(NetClientState *nc)
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static uint64_t nvnet_io_read(void *opaque, hwaddr addr, unsigned int size)
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{
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NVNET_DPRINTF("nvnet io: read [0x%llx]\n", addr);
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return 0;
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uint64_t r = 0;
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trace_nvnet_io_read(addr, size, r);
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return r;
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}
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static void nvnet_io_write(void *opaque,
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hwaddr addr, uint64_t val, unsigned int size)
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{
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NVNET_DPRINTF("nvnet io: [0x%llx] = 0x%llx\n", addr, val);
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trace_nvnet_io_write(addr, size, val);
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}
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static const MemoryRegionOps nvnet_io_ops = {
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@ -992,7 +994,6 @@ static void nvnet_hex_dump(NvNetState *s, const uint8_t *buf, int size)
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}
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}
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#ifdef DEBUG
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/*
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* Return register name given the offset of the device register.
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*/
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@ -1060,6 +1061,7 @@ static const char *nvnet_get_mii_reg_name(uint8_t reg)
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}
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}
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#ifdef DEBUG
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static void nvnet_dump_ring_descriptors(NvNetState *s)
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{
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struct RingDesc desc;
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@ -0,0 +1,9 @@
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# See docs/devel/tracing.rst for syntax documentation.
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# nvnet.c
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nvnet_mii_read(unsigned int phy_addr, uint32_t addr, const char *name, uint64_t val) "phy %d addr 0x%"PRIx32" %s val 0x%"PRIx64
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nvnet_mii_write(unsigned int phy_addr, uint32_t addr, const char *name, uint64_t val) "phy %d addr 0x%"PRIx32" %s val 0x%"PRIx64
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nvnet_reg_read(uint32_t addr, const char *name, unsigned int size, uint64_t val) "addr 0x%"PRIx32" %s size %d val 0x%"PRIx64
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nvnet_reg_write(uint32_t addr, const char *name, unsigned int size, uint64_t val) "addr 0x%"PRIx32" %s size %d val 0x%"PRIx64
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nvnet_io_read(uint32_t addr, unsigned int size, uint64_t val) "addr 0x%"PRIx32" size %d val 0x%"PRIx64
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nvnet_io_write(uint32_t addr, unsigned int size, uint64_t val) "addr 0x%"PRIx32" size %d val 0x%"PRIx64
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@ -0,0 +1 @@
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#include "trace/trace-hw_xbox.h"
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@ -2188,6 +2188,7 @@ if have_system
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'hw/remote',
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'hw/xbox/nv2a',
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'hw/xbox/mcpx',
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'hw/xbox',
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]
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endif
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if have_system or have_user
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