From 2aa469ff5fde3f1c59b14ddf48d58018e2f03982 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 27 May 2022 11:17:48 -0700 Subject: [PATCH] target/arm: Use TRANS_FEAT for RAX1 The decode for RAX1 sets esz to MO_8, because that's what we use by default for "no esz present". We changed that to MO_64 during translation because it is more logical for the operation. However, the esz argument to gen_gvec_rax1 is unused and forces MO_64 within that function, so there is no need to do it here as well. Simplify to use gen_gvec_fn_arg_zzz and TRANS_FEAT. Signed-off-by: Richard Henderson Message-id: 20220527181907.189259-36-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate-sve.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index e92fef2304..36d739d7b2 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -7814,13 +7814,7 @@ TRANS_FEAT(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, TRANS_FEAT(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, gen_helper_crypto_sm4ekey, a, 0) -static bool trans_RAX1(DisasContext *s, arg_rrr_esz *a) -{ - if (!dc_isar_feature(aa64_sve2_sha3, s)) { - return false; - } - return gen_gvec_fn_zzz(s, gen_gvec_rax1, MO_64, a->rd, a->rn, a->rm); -} +TRANS_FEAT(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz, gen_gvec_rax1, a) static bool trans_FCVTNT_sh(DisasContext *s, arg_rpr_esz *a) {