From 29c4a3363bf287bb9a7b0342b1bc2dba3661c96c Mon Sep 17 00:00:00 2001 From: Fabiano Rosas Date: Fri, 17 Dec 2021 17:57:18 +0100 Subject: [PATCH] Revert "target/ppc: Move SPR_DSISR setting to powerpc_excp" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit 336e91f85332dda0ede4c1d15b87a19a0fb898a2. It breaks the --disable-tcg build: ../target/ppc/excp_helper.c:463:29: error: implicit declaration of function ‘cpu_ldl_code’ [-Werror=implicit-function-declaration] We should not have TCG code in powerpc_excp because some kvm-only routines use it indirectly to dispatch interrupts. See kvm_handle_debug, spapr_mce_req_event and spapr_do_system_reset_on_cpu. We can re-introduce the change once we have split the interrupt injection code between KVM and TCG. Signed-off-by: Fabiano Rosas Message-Id: <20211209173323.2166642-1-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/excp_helper.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index feb3fd42e2..6ba0840e99 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -464,15 +464,13 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) break; } case POWERPC_EXCP_ALIGN: /* Alignment exception */ + /* Get rS/rD and rA from faulting opcode */ /* - * Get rS/rD and rA from faulting opcode. - * Note: We will only invoke ALIGN for atomic operations, - * so all instructions are X-form. + * Note: the opcode fields will not be set properly for a + * direct store load/store, but nobody cares as nobody + * actually uses direct store segments. */ - { - uint32_t insn = cpu_ldl_code(env, env->nip); - env->spr[SPR_DSISR] |= (insn & 0x03FF0000) >> 16; - } + env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; break; case POWERPC_EXCP_PROGRAM: /* Program exception */ switch (env->error_code & ~0xF) { @@ -1441,6 +1439,11 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int mmu_idx, uintptr_t retaddr) { CPUPPCState *env = cs->env_ptr; + uint32_t insn; + + /* Restore state and reload the insn we executed, for filling in DSISR. */ + cpu_restore_state(cs, retaddr, true); + insn = cpu_ldl_code(env, env->nip); switch (env->mmu_model) { case POWERPC_MMU_SOFT_4xx: @@ -1456,8 +1459,8 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, } cs->exception_index = POWERPC_EXCP_ALIGN; - env->error_code = 0; - cpu_loop_exit_restore(cs, retaddr); + env->error_code = insn & 0x03FF0000; + cpu_loop_exit(cs); } #endif /* CONFIG_TCG */ #endif /* !CONFIG_USER_ONLY */