From 50fab4cc672233fee22fff2cf51543af57602c7d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 2 Mar 2021 09:00:42 +0100 Subject: [PATCH 1/3] hw/isa/Kconfig: Add missing dependency VIA VT82C686 -> APM MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit TYPE_VIA_PM calls apm_init() in via_pm_realize(), so requires APM to be selected. Reported-by: BALATON Zoltan Fixes: dd0ff8191ab ("isa: express SuperIO dependencies with Kconfig") Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210302080531.913802-1-f4bug@amsat.org> --- hw/isa/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index 2691eae2f0..55e0003ce4 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -48,6 +48,7 @@ config VT82C686 select SERIAL_ISA select FDC select USB_UHCI + select APM config SMC37C669 bool From 62271205bcfaee440d06c06060ee79dac657caff Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Wed, 24 Mar 2021 14:54:43 +0100 Subject: [PATCH 2/3] hw/isa/piix4: Migrate Reset Control Register MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When adding the Reset register in commit 5790b757cfb we forgot to migrate it. While it is possible a VM using the PIIX4 is migrated just after requesting a system shutdown, it is very unlikely. However when restoring a migrated VM, we might have the RCR bit #4 set on the stack and when the VM resume it directly shutdowns. Add a post_load() migration handler and set the default RCR value to 0 for earlier versions, assuming the VM was not going to shutdown before migration. Fixes: 5790b757cfb ("piix4: Add the Reset Control Register") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Dr. David Alan Gilbert Message-Id: <20210324200334.729899-1-f4bug@amsat.org> --- hw/isa/piix4.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index a50d97834c..b3b6a4378a 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -93,12 +93,25 @@ static void piix4_isa_reset(DeviceState *dev) pci_conf[0xae] = 0x00; } +static int piix4_ide_post_load(void *opaque, int version_id) +{ + PIIX4State *s = opaque; + + if (version_id == 2) { + s->rcr = 0; + } + + return 0; +} + static const VMStateDescription vmstate_piix4 = { .name = "PIIX4", - .version_id = 2, + .version_id = 3, .minimum_version_id = 2, + .post_load = piix4_ide_post_load, .fields = (VMStateField[]) { VMSTATE_PCI_DEVICE(dev, PIIX4State), + VMSTATE_UINT8_V(rcr, PIIX4State, 3), VMSTATE_END_OF_LIST() } }; From f4349ba966abfe39f5d98694abd7c7551d5c8c02 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 6 Apr 2021 22:26:21 +0200 Subject: [PATCH 3/3] target/mips: Fix TCG temporary leak in gen_cache_operation() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix a TCG temporary leak when translating CACHE opcode. Fixes: 0d74a222c27 ("make ITC Configuration Tags accessible to the CPU") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210406202857.1440744-1-f4bug@amsat.org> --- target/mips/translate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index c518bf3963..71fa5ec197 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -12804,6 +12804,8 @@ static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base, TCGv t1 = tcg_temp_new(); gen_base_offset_addr(ctx, t1, base, offset); gen_helper_cache(cpu_env, t1, t0); + tcg_temp_free(t1); + tcg_temp_free_i32(t0); } #if defined(TARGET_MIPS64)