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target-arm queue: 

* s390: convert s390 virtio-ccw and CPU to three-phase reset
  * reset: remove now-unused device_class_set_parent_reset()
  * reset: introduce device_class_set_legacy_reset()
  * reset: remove unneeded transitional machinery
  * kvm: Use 'unsigned long' for request argument in functions wrapping ioctl()
  * hvf: arm: Implement and use hvf_get_physical_address_range
    so VMs can have larger-than-36-bit IPA spaces when the host
    supports this
  * target/arm/tcg: refine cache descriptions with a wrapper
  * hw/net/can/xlnx-versal-canfd: fix various bugs
  * MAINTAINERS: update versal, CAN maintainer entries
  * hw/intc/arm_gic: fix spurious level triggered interrupts
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Merge tag 'pull-target-arm-20240913' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * s390: convert s390 virtio-ccw and CPU to three-phase reset
 * reset: remove now-unused device_class_set_parent_reset()
 * reset: introduce device_class_set_legacy_reset()
 * reset: remove unneeded transitional machinery
 * kvm: Use 'unsigned long' for request argument in functions wrapping ioctl()
 * hvf: arm: Implement and use hvf_get_physical_address_range
   so VMs can have larger-than-36-bit IPA spaces when the host
   supports this
 * target/arm/tcg: refine cache descriptions with a wrapper
 * hw/net/can/xlnx-versal-canfd: fix various bugs
 * MAINTAINERS: update versal, CAN maintainer entries
 * hw/intc/arm_gic: fix spurious level triggered interrupts

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# gpg: Signature made Fri 13 Sep 2024 16:13:13 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20240913' of https://git.linaro.org/people/pmaydell/qemu-arm: (27 commits)
  hw/intc/arm_gic: fix spurious level triggered interrupts
  MAINTAINERS: Add my-self as CAN maintainer
  MAINTAINERS: Update Xilinx Versal OSPI maintainer's email address
  MAINTAINERS: Remove Vikram Garhwal as maintainer
  hw/net/can/xlnx-versal-canfd: Fix FIFO issues
  hw/net/can/xlnx-versal-canfd: Simplify DLC conversions
  hw/net/can/xlnx-versal-canfd: Fix byte ordering
  hw/net/can/xlnx-versal-canfd: Handle flags correctly
  hw/net/can/xlnx-versal-canfd: Translate CAN ID registers
  hw/net/can/xlnx-versal-canfd: Fix CAN FD flag check
  hw/net/can/xlnx-versal-canfd: Fix interrupt level
  target/arm/tcg: refine cache descriptions with a wrapper
  hvf: arm: Implement and use hvf_get_physical_address_range
  hvf: Split up hv_vm_create logic per arch
  hw/boards: Add hvf_get_physical_address_range to MachineClass
  kvm: Use 'unsigned long' for request argument in functions wrapping ioctl()
  hw/core/resettable: Remove transitional_function machinery
  hw/core/qdev: Simplify legacy_reset handling
  hw: Remove device_phases_reset()
  hw: Rename DeviceClass::reset field to legacy_reset
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2024-09-13 16:14:33 +01:00
parent 63731c346f 110684c9a6
commit 28ae3179fc
442 changed files with 977 additions and 820 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
MAINTAINERS
View File

@ -1058,7 +1058,7 @@ F: include/hw/display/dpcd.h
F: docs/system/arm/xlnx-versal-virt.rst
Xilinx Versal OSPI
M: Francisco Iglesias <francisco.iglesias@xilinx.com>
M: Francisco Iglesias <francisco.iglesias@amd.com>
S: Maintained
F: hw/ssi/xlnx-versal-ospi.c
F: include/hw/ssi/xlnx-versal-ospi.h
@ -1951,7 +1951,6 @@ F: tests/qtest/intel-hda-test.c
F: tests/qtest/fuzz-sb16-test.c
Xilinx CAN
M: Vikram Garhwal <vikram.garhwal@amd.com>
M: Francisco Iglesias <francisco.iglesias@amd.com>
S: Maintained
F: hw/net/can/xlnx-*
@ -2708,7 +2707,7 @@ F: include/hw/rx/
CAN bus subsystem and hardware
M: Pavel Pisa <pisa@cmp.felk.cvut.cz>
M: Vikram Garhwal <fnu.vikram@xilinx.com>
M: Francisco Iglesias <francisco.iglesias@amd.com>
S: Maintained
W: https://canbus.pages.fel.cvut.cz/
F: net/can/*

16
accel/hvf/hvf-accel-ops.c
View File

@ -53,6 +53,7 @@
#include "exec/address-spaces.h"
#include "exec/exec-all.h"
#include "gdbstub/enums.h"
#include "hw/boards.h"
#include "sysemu/cpus.h"
#include "sysemu/hvf.h"
#include "sysemu/hvf_int.h"
@ -61,10 +62,6 @@
HVFState *hvf_state;
#ifdef __aarch64__
#define HV_VM_DEFAULT NULL
#endif
/* Memory slots */
hvf_slot *hvf_find_overlap_slot(uint64_t start, uint64_t size)
@ -323,8 +320,17 @@ static int hvf_accel_init(MachineState *ms)
int x;
hv_return_t ret;
HVFState *s;
int pa_range = 36;
MachineClass *mc = MACHINE_GET_CLASS(ms);
ret = hv_vm_create(HV_VM_DEFAULT);
if (mc->hvf_get_physical_address_range) {
pa_range = mc->hvf_get_physical_address_range(ms);
if (pa_range < 0) {
return -EINVAL;
}
}
ret = hvf_arch_vm_create(ms, (uint32_t)pa_range);
assert_hvf_ok(ret);
s = g_new0(HVFState, 1);

8
accel/kvm/kvm-all.c
View File

@ -3170,7 +3170,7 @@ int kvm_cpu_exec(CPUState *cpu)
return ret;
}
int kvm_ioctl(KVMState *s, int type, ...)
int kvm_ioctl(KVMState *s, unsigned long type, ...)
{
int ret;
void *arg;
@ -3188,7 +3188,7 @@ int kvm_ioctl(KVMState *s, int type, ...)
return ret;
}
int kvm_vm_ioctl(KVMState *s, int type, ...)
int kvm_vm_ioctl(KVMState *s, unsigned long type, ...)
{
int ret;
void *arg;
@ -3208,7 +3208,7 @@ int kvm_vm_ioctl(KVMState *s, int type, ...)
return ret;
}
int kvm_vcpu_ioctl(CPUState *cpu, int type, ...)
int kvm_vcpu_ioctl(CPUState *cpu, unsigned long type, ...)
{
int ret;
void *arg;
@ -3228,7 +3228,7 @@ int kvm_vcpu_ioctl(CPUState *cpu, int type, ...)
return ret;
}
int kvm_device_ioctl(int fd, int type, ...)
int kvm_device_ioctl(int fd, unsigned long type, ...)
{
int ret;
void *arg;

8
accel/kvm/trace-events
View File

@ -1,11 +1,11 @@
# See docs/devel/tracing.rst for syntax documentation.
# kvm-all.c
kvm_ioctl(int type, void *arg) "type 0x%x, arg %p"
kvm_vm_ioctl(int type, void *arg) "type 0x%x, arg %p"
kvm_vcpu_ioctl(int cpu_index, int type, void *arg) "cpu_index %d, type 0x%x, arg %p"
kvm_ioctl(unsigned long type, void *arg) "type 0x%lx, arg %p"
kvm_vm_ioctl(unsigned long type, void *arg) "type 0x%lx, arg %p"
kvm_vcpu_ioctl(int cpu_index, unsigned long type, void *arg) "cpu_index %d, type 0x%lx, arg %p"
kvm_run_exit(int cpu_index, uint32_t reason) "cpu_index %d, reason %d"
kvm_device_ioctl(int fd, int type, void *arg) "dev fd %d, type 0x%x, arg %p"
kvm_device_ioctl(int fd, unsigned long type, void *arg) "dev fd %d, type 0x%lx, arg %p"
kvm_failed_reg_get(uint64_t id, const char *msg) "Warning: Unable to retrieve ONEREG %" PRIu64 " from KVM: %s"
kvm_failed_reg_set(uint64_t id, const char *msg) "Warning: Unable to set ONEREG %" PRIu64 " to KVM: %s"
kvm_init_vcpu(int cpu_index, unsigned long arch_cpu_id) "index: %d id: %lu"

10
docs/devel/reset.rst
View File

@ -44,6 +44,16 @@ The Resettable interface handles reset types with an enum ``ResetType``:
value on each cold reset, such as RNG seed information, and which they
must not reinitialize on a snapshot-load reset.
``RESET_TYPE_S390_CPU_NORMAL``
This is only used for S390 CPU objects; it clears interrupts, stops
processing, and clears the TLB, but does not touch register contents.
``RESET_TYPE_S390_CPU_INITIAL``
This is only used for S390 CPU objects; it does everything
``RESET_TYPE_S390_CPU_NORMAL`` does and also clears the PSW, prefix,
FPC, timer and control registers. It does not touch gprs, fprs or acrs.
Devices which implement reset methods must treat any unknown ``ResetType``
as equivalent to ``RESET_TYPE_COLD``; this will reduce the amount of
existing code we need to change if we add more types in future.

2
hw/acpi/erst.c
View File

@ -1030,7 +1030,7 @@ static void erst_class_init(ObjectClass *klass, void *data)
k->device_id = PCI_DEVICE_ID_REDHAT_ACPI_ERST;
k->revision = 0x00;
k->class_id = PCI_CLASS_OTHERS;
dc->reset = erst_reset;
device_class_set_legacy_reset(dc, erst_reset);
dc->vmsd = &erst_vmstate;
dc->user_creatable = true;
dc->hotpluggable = false;

2
hw/acpi/piix4.c
View File

@ -633,7 +633,7 @@ static void piix4_pm_class_init(ObjectClass *klass, void *data)
k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
k->revision = 0x03;
k->class_id = PCI_CLASS_BRIDGE_OTHER;
dc->reset = piix4_pm_reset;
device_class_set_legacy_reset(dc, piix4_pm_reset);
dc->desc = "PM";
dc->vmsd = &vmstate_acpi;
device_class_set_props(dc, piix4_pm_properties);

2
hw/adc/aspeed_adc.c
View File

@ -297,7 +297,7 @@ static void aspeed_adc_engine_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = aspeed_adc_engine_realize;
dc->reset = aspeed_adc_engine_reset;
device_class_set_legacy_reset(dc, aspeed_adc_engine_reset);
device_class_set_props(dc, aspeed_adc_engine_properties);
dc->desc = "Aspeed Analog-to-Digital Engine";
dc->vmsd = &vmstate_aspeed_adc_engine;

2
hw/adc/max111x.c
View File

@ -183,7 +183,7 @@ static void max111x_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
k->transfer = max111x_transfer;
dc->reset = max111x_reset;
device_class_set_legacy_reset(dc, max111x_reset);
dc->vmsd = &vmstate_max111x;
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
}

2
hw/adc/stm32f2xx_adc.c
View File

@ -288,7 +288,7 @@ static void stm32f2xx_adc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = stm32f2xx_adc_reset;
device_class_set_legacy_reset(dc, stm32f2xx_adc_reset);
dc->vmsd = &vmstate_stm32f2xx_adc;
}

2
hw/adc/zynq-xadc.c
View File

@ -286,7 +286,7 @@ static void zynq_xadc_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->vmsd = &vmstate_zynq_xadc;
dc->reset = zynq_xadc_reset;
device_class_set_legacy_reset(dc, zynq_xadc_reset);
}
static const TypeInfo zynq_xadc_info = {

2
hw/arm/armsse.c
View File

@ -1700,7 +1700,7 @@ static void armsse_class_init(ObjectClass *klass, void *data)
dc->realize = armsse_realize;
dc->vmsd = &armsse_vmstate;
device_class_set_props(dc, info->props);
dc->reset = armsse_reset;
device_class_set_legacy_reset(dc, armsse_reset);
iic->check = armsse_idau_check;
asc->info = info;
}

2
hw/arm/highbank.c
View File

@ -145,7 +145,7 @@ static void highbank_regs_class_init(ObjectClass *klass, void *data)
dc->desc = "Calxeda Highbank registers";
dc->vmsd = &vmstate_highbank_regs;
dc->reset = highbank_regs_reset;
device_class_set_legacy_reset(dc, highbank_regs_reset);
}
static const TypeInfo highbank_regs_info = {

6
hw/arm/musicpal.c
View File

@ -411,7 +411,7 @@ static void mv88w8618_pic_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = mv88w8618_pic_reset;
device_class_set_legacy_reset(dc, mv88w8618_pic_reset);
dc->vmsd = &mv88w8618_pic_vmsd;
}
@ -605,7 +605,7 @@ static void mv88w8618_pit_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = mv88w8618_pit_reset;
device_class_set_legacy_reset(dc, mv88w8618_pit_reset);
dc->vmsd = &mv88w8618_pit_vmsd;
}
@ -1030,7 +1030,7 @@ static void musicpal_gpio_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = musicpal_gpio_reset;
device_class_set_legacy_reset(dc, musicpal_gpio_reset);
dc->vmsd = &musicpal_gpio_vmsd;
}

4
hw/arm/pxa2xx.c
View File

@ -2051,7 +2051,7 @@ static void pxa2xx_fir_class_init(ObjectClass *klass, void *data)
dc->realize = pxa2xx_fir_realize;
dc->vmsd = &pxa2xx_fir_vmsd;
device_class_set_props(dc, pxa2xx_fir_properties);
dc->reset = pxa2xx_fir_reset;
device_class_set_legacy_reset(dc, pxa2xx_fir_reset);
}
static const TypeInfo pxa2xx_fir_info = {
@ -2369,7 +2369,7 @@ static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = pxa2xx_ssp_reset;
device_class_set_legacy_reset(dc, pxa2xx_ssp_reset);
dc->vmsd = &vmstate_pxa2xx_ssp;
}

4
hw/arm/strongarm.c
View File

@ -1342,7 +1342,7 @@ static void strongarm_uart_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->desc = "StrongARM UART controller";
dc->reset = strongarm_uart_reset;
device_class_set_legacy_reset(dc, strongarm_uart_reset);
dc->vmsd = &vmstate_strongarm_uart_regs;
device_class_set_props(dc, strongarm_uart_properties);
dc->realize = strongarm_uart_realize;
@ -1595,7 +1595,7 @@ static void strongarm_ssp_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->desc = "StrongARM SSP controller";
dc->reset = strongarm_ssp_reset;
device_class_set_legacy_reset(dc, strongarm_ssp_reset);
dc->vmsd = &vmstate_strongarm_ssp_regs;
}

38
hw/arm/virt.c
View File

@ -66,6 +66,7 @@
#include "hw/intc/arm_gicv3_its_common.h"
#include "hw/irq.h"
#include "kvm_arm.h"
#include "hvf_arm.h"
#include "hw/firmware/smbios.h"
#include "qapi/visitor.h"
#include "qapi/qapi-visit-common.h"
@ -2111,7 +2112,8 @@ static void machvirt_init(MachineState *machine)
/*
* In accelerated mode, the memory map is computed earlier in kvm_type()
* to create a VM with the right number of IPA bits.
* for Linux, or hvf_get_physical_address_range() for macOS to create a
* VM with the right number of IPA bits.
*/
if (!vms->memmap) {
Object *cpuobj;
@ -3031,6 +3033,39 @@ static int virt_kvm_type(MachineState *ms, const char *type_str)
return fixed_ipa ? 0 : requested_pa_size;
}
static int virt_hvf_get_physical_address_range(MachineState *ms)
{
VirtMachineState *vms = VIRT_MACHINE(ms);
int default_ipa_size = hvf_arm_get_default_ipa_bit_size();
int max_ipa_size = hvf_arm_get_max_ipa_bit_size();
/* We freeze the memory map to compute the highest gpa */
virt_set_memmap(vms, max_ipa_size);
int requested_ipa_size = 64 - clz64(vms->highest_gpa);
/*
* If we're <= the default IPA size just use the default.
* If we're above the default but below the maximum, round up to
* the maximum. hvf_arm_get_max_ipa_bit_size() conveniently only
* returns values that are valid ARM PARange values.
*/
if (requested_ipa_size <= default_ipa_size) {
requested_ipa_size = default_ipa_size;
} else if (requested_ipa_size <= max_ipa_size) {
requested_ipa_size = max_ipa_size;
} else {
error_report("-m and ,maxmem option values "
"require an IPA range (%d bits) larger than "
"the one supported by the host (%d bits)",
requested_ipa_size, max_ipa_size);
return -1;
}
return requested_ipa_size;
}
static void virt_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@ -3090,6 +3125,7 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
mc->valid_cpu_types = valid_cpu_types;
mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
mc->kvm_type = virt_kvm_type;
mc->hvf_get_physical_address_range = virt_hvf_get_physical_address_range;
assert(!mc->get_hotplug_handler);
mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
hc->pre_plug = virt_machine_device_pre_plug_cb;

2
hw/audio/ac97.c
View File

@ -1344,7 +1344,7 @@ static void ac97_class_init(ObjectClass *klass, void *data)
dc->desc = "Intel 82801AA AC97 Audio";
dc->vmsd = &vmstate_ac97;
device_class_set_props(dc, ac97_properties);
dc->reset = ac97_on_reset;
device_class_set_legacy_reset(dc, ac97_on_reset);
}
static const TypeInfo ac97_info = {

2
hw/audio/cs4231.c
View File

@ -164,7 +164,7 @@ static void cs4231_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = cs_reset;
device_class_set_legacy_reset(dc, cs_reset);
dc->vmsd = &vmstate_cs4231;
}

2
hw/audio/cs4231a.c
View File

@ -702,7 +702,7 @@ static void cs4231a_class_initfn (ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS (klass);
dc->realize = cs4231a_realizefn;
dc->reset = cs4231a_reset;
device_class_set_legacy_reset(dc, cs4231a_reset);
set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
dc->desc = "Crystal Semiconductor CS4231A";
dc->vmsd = &vmstate_cs4231a;

2
hw/audio/es1370.c
View File

@ -888,7 +888,7 @@ static void es1370_class_init (ObjectClass *klass, void *data)
set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
dc->desc = "ENSONIQ AudioPCI ES1370";
dc->vmsd = &vmstate_es1370;
dc->reset = es1370_on_reset;
device_class_set_legacy_reset(dc, es1370_on_reset);
device_class_set_props(dc, es1370_properties);
}

2
hw/audio/hda-codec.c
View File

@ -910,7 +910,7 @@ static void hda_audio_base_class_init(ObjectClass *klass, void *data)
k->command = hda_audio_command;
k->stream = hda_audio_stream;
set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
dc->reset = hda_audio_reset;
device_class_set_legacy_reset(dc, hda_audio_reset);
dc->vmsd = &vmstate_hda_audio;
device_class_set_props(dc, hda_audio_properties);
}

2
hw/audio/intel-hda.c
View File

@ -1231,7 +1231,7 @@ static void intel_hda_class_init(ObjectClass *klass, void *data)
k->exit = intel_hda_exit;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO;
dc->reset = intel_hda_reset;
device_class_set_legacy_reset(dc, intel_hda_reset);
dc->vmsd = &vmstate_intel_hda;
device_class_set_props(dc, intel_hda_properties);
}

2
hw/audio/marvell_88w8618.c
View File

@ -292,7 +292,7 @@ static void mv88w8618_audio_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = mv88w8618_audio_realize;
dc->reset = mv88w8618_audio_reset;
device_class_set_legacy_reset(dc, mv88w8618_audio_reset);
dc->vmsd = &mv88w8618_audio_vmsd;
dc->user_creatable = false;
}

2
hw/audio/pl041.c
View File

@ -639,7 +639,7 @@ static void pl041_device_class_init(ObjectClass *klass, void *data)
dc->realize = pl041_realize;
set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
dc->reset = pl041_device_reset;
device_class_set_legacy_reset(dc, pl041_device_reset);
dc->vmsd = &vmstate_pl041;
device_class_set_props(dc, pl041_device_properties);
}

2
hw/audio/via-ac97.c
View File

@ -478,7 +478,7 @@ static void via_ac97_class_init(ObjectClass *klass, void *data)
device_class_set_props(dc, via_ac97_properties);
set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
dc->desc = "VIA AC97";
dc->reset = via_ac97_reset;
device_class_set_legacy_reset(dc, via_ac97_reset);
/* Reason: Part of a south bridge chip */
dc->user_creatable = false;
}

2
hw/block/fdc-isa.c
View File

@ -307,7 +307,7 @@ static void isabus_fdc_class_init(ObjectClass *klass, void *data)
dc->desc = "virtual floppy controller";
dc->realize = isabus_fdc_realize;
dc->fw_name = "fdc";
dc->reset = fdctrl_external_reset_isa;
device_class_set_legacy_reset(dc, fdctrl_external_reset_isa);
dc->vmsd = &vmstate_isa_fdc;
adevc->build_dev_aml = build_fdc_aml;
device_class_set_props(dc, isa_fdc_properties);

2
hw/block/fdc-sysbus.c
View File

@ -181,7 +181,7 @@ static void sysbus_fdc_common_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = sysbus_fdc_realize;
dc->reset = fdctrl_external_reset_sysbus;
device_class_set_legacy_reset(dc, fdctrl_external_reset_sysbus);
dc->vmsd = &vmstate_sysbus_fdc;
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}

2
hw/block/m25p80.c
View File

@ -1824,7 +1824,7 @@ static void m25p80_class_init(ObjectClass *klass, void *data)
k->cs_polarity = SSI_CS_LOW;
dc->vmsd = &vmstate_m25p80;
device_class_set_props(dc, m25p80_properties);
dc->reset = m25p80_reset;
device_class_set_legacy_reset(dc, m25p80_reset);
mc->pi = data;
}

2
hw/block/nand.c
View File

@ -457,7 +457,7 @@ static void nand_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = nand_realize;
dc->reset = nand_reset;
device_class_set_legacy_reset(dc, nand_reset);
dc->vmsd = &vmstate_nand;
device_class_set_props(dc, nand_properties);
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);

2
hw/block/onenand.c
View File

@ -846,7 +846,7 @@ static void onenand_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = onenand_realize;
dc->reset = onenand_system_reset;
device_class_set_legacy_reset(dc, onenand_system_reset);
device_class_set_props(dc, onenand_properties);
}

2
hw/block/pflash_cfi01.c
View File

@ -940,7 +940,7 @@ static void pflash_cfi01_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = pflash_cfi01_system_reset;
device_class_set_legacy_reset(dc, pflash_cfi01_system_reset);
dc->realize = pflash_cfi01_realize;
device_class_set_props(dc, pflash_cfi01_properties);
dc->vmsd = &vmstate_pflash;

2
hw/block/pflash_cfi02.c
View File

@ -974,7 +974,7 @@ static void pflash_cfi02_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = pflash_cfi02_realize;
dc->reset = pflash_cfi02_reset;
device_class_set_legacy_reset(dc, pflash_cfi02_reset);
dc->unrealize = pflash_cfi02_unrealize;
device_class_set_props(dc, pflash_cfi02_properties);
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);

2
hw/block/swim.c
View File

@ -556,7 +556,7 @@ static void sysbus_swim_class_init(ObjectClass *oc, void *data)
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = sysbus_swim_realize;
dc->reset = sysbus_swim_reset;
device_class_set_legacy_reset(dc, sysbus_swim_reset);
dc->vmsd = &vmstate_sysbus_swim;
}

2
hw/char/avr_usart.c
View File

@ -300,7 +300,7 @@ static void avr_usart_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = avr_usart_reset;
device_class_set_legacy_reset(dc, avr_usart_reset);
device_class_set_props(dc, avr_usart_properties);
dc->realize = avr_usart_realize;
}

2
hw/char/cmsdk-apb-uart.c
View File

@ -389,7 +389,7 @@ static void cmsdk_apb_uart_class_init(ObjectClass *klass, void *data)
dc->realize = cmsdk_apb_uart_realize;
dc->vmsd = &cmsdk_apb_uart_vmstate;
dc->reset = cmsdk_apb_uart_reset;
device_class_set_legacy_reset(dc, cmsdk_apb_uart_reset);
device_class_set_props(dc, cmsdk_apb_uart_properties);
}

2
hw/char/digic-uart.c
View File

@ -182,7 +182,7 @@ static void digic_uart_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = digic_uart_realize;
dc->reset = digic_uart_reset;
device_class_set_legacy_reset(dc, digic_uart_reset);
dc->vmsd = &vmstate_digic_uart;
device_class_set_props(dc, digic_uart_properties);
}

2
hw/char/escc.c
View File

@ -1062,7 +1062,7 @@ static void escc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = escc_reset;
device_class_set_legacy_reset(dc, escc_reset);
dc->realize = escc_realize;
dc->vmsd = &vmstate_escc;
device_class_set_props(dc, escc_properties);

2
hw/char/etraxfs_ser.c
View File

@ -246,7 +246,7 @@ static void etraxfs_ser_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = etraxfs_ser_reset;
device_class_set_legacy_reset(dc, etraxfs_ser_reset);
device_class_set_props(dc, etraxfs_ser_properties);
dc->realize = etraxfs_ser_realize;
}

2
hw/char/exynos4210_uart.c
View File

@ -717,7 +717,7 @@ static void exynos4210_uart_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = exynos4210_uart_realize;
dc->reset = exynos4210_uart_reset;
device_class_set_legacy_reset(dc, exynos4210_uart_reset);
device_class_set_props(dc, exynos4210_uart_properties);
dc->vmsd = &vmstate_exynos4210_uart;
}

2
hw/char/goldfish_tty.c
View File

@ -262,7 +262,7 @@ static void goldfish_tty_class_init(ObjectClass *oc, void *data)
DeviceClass *dc = DEVICE_CLASS(oc);
device_class_set_props(dc, goldfish_tty_properties);
dc->reset = goldfish_tty_reset;
device_class_set_legacy_reset(dc, goldfish_tty_reset);
dc->realize = goldfish_tty_realize;
dc->unrealize = goldfish_tty_unrealize;
dc->vmsd = &vmstate_goldfish_tty;

2
hw/char/grlib_apbuart.c
View File

@ -287,7 +287,7 @@ static void grlib_apbuart_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = grlib_apbuart_realize;
dc->reset = grlib_apbuart_reset;
device_class_set_legacy_reset(dc, grlib_apbuart_reset);
device_class_set_props(dc, grlib_apbuart_properties);
}

2
hw/char/ibex_uart.c
View File

@ -547,7 +547,7 @@ static void ibex_uart_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = ibex_uart_reset;
device_class_set_legacy_reset(dc, ibex_uart_reset);
dc->realize = ibex_uart_realize;
dc->vmsd = &vmstate_ibex_uart;
device_class_set_props(dc, ibex_uart_properties);

2
hw/char/imx_serial.c
View File

@ -449,7 +449,7 @@ static void imx_serial_class_init(ObjectClass *klass, void *data)
dc->realize = imx_serial_realize;
dc->vmsd = &vmstate_imx_serial;
dc->reset = imx_serial_reset_at_boot;
device_class_set_legacy_reset(dc, imx_serial_reset_at_boot);
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
dc->desc = "i.MX series UART";
device_class_set_props(dc, imx_serial_properties);

2
hw/char/mcf_uart.c
View File

@ -322,7 +322,7 @@ static void mcf_uart_class_init(ObjectClass *oc, void *data)
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = mcf_uart_realize;
dc->reset = mcf_uart_reset;
device_class_set_legacy_reset(dc, mcf_uart_reset);
device_class_set_props(dc, mcf_uart_properties);
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}

2
hw/char/mchp_pfsoc_mmuart.c
View File

@ -126,7 +126,7 @@ static void mchp_pfsoc_mmuart_class_init(ObjectClass *oc, void *data)
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = mchp_pfsoc_mmuart_realize;
dc->reset = mchp_pfsoc_mmuart_reset;
device_class_set_legacy_reset(dc, mchp_pfsoc_mmuart_reset);
dc->vmsd = &mchp_pfsoc_mmuart_vmstate;
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}

2
hw/char/nrf51_uart.c
View File

@ -313,7 +313,7 @@ static void nrf51_uart_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = nrf51_uart_reset;
device_class_set_legacy_reset(dc, nrf51_uart_reset);
dc->realize = nrf51_uart_realize;
device_class_set_props(dc, nrf51_uart_properties);
dc->vmsd = &nrf51_uart_vmstate;

2
hw/char/pl011.c
View File

@ -629,7 +629,7 @@ static void pl011_class_init(ObjectClass *oc, void *data)
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = pl011_realize;
dc->reset = pl011_reset;
device_class_set_legacy_reset(dc, pl011_reset);
dc->vmsd = &vmstate_pl011;
device_class_set_props(dc, pl011_properties);
}

2
hw/char/renesas_sci.c
View File

@ -331,7 +331,7 @@ static void rsci_class_init(ObjectClass *klass, void *data)
dc->realize = rsci_realize;
dc->vmsd = &vmstate_rsci;
dc->reset = rsci_reset;
device_class_set_legacy_reset(dc, rsci_reset);
device_class_set_props(dc, rsci_properties);
}

2
hw/char/sclpconsole-lm.c
View File

@ -346,7 +346,7 @@ static void console_class_init(ObjectClass *klass, void *data)
SCLPEventClass *ec = SCLP_EVENT_CLASS(klass);
device_class_set_props(dc, console_properties);
dc->reset = console_reset;
device_class_set_legacy_reset(dc, console_reset);
dc->vmsd = &vmstate_sclplmconsole;
ec->init = console_init;
ec->get_send_mask = send_mask;

2
hw/char/sclpconsole.c
View File

@ -262,7 +262,7 @@ static void console_class_init(ObjectClass *klass, void *data)
SCLPEventClass *ec = SCLP_EVENT_CLASS(klass);
device_class_set_props(dc, console_properties);
dc->reset = console_reset;
device_class_set_legacy_reset(dc, console_reset);
dc->vmsd = &vmstate_sclpconsole;
ec->init = console_init;
ec->get_send_mask = send_mask;

2
hw/char/sh_serial.c
View File

@ -459,7 +459,7 @@ static void sh_serial_class_init(ObjectClass *oc, void *data)
device_class_set_props(dc, sh_serial_properties);
dc->realize = sh_serial_realize;
dc->reset = sh_serial_reset;
device_class_set_legacy_reset(dc, sh_serial_reset);
/* Reason: part of SuperH CPU/SoC, needs to be wired up */
dc->user_creatable = false;
}

2
hw/char/shakti_uart.c
View File

@ -165,7 +165,7 @@ static Property shakti_uart_properties[] = {
static void shakti_uart_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = shakti_uart_reset;
device_class_set_legacy_reset(dc, shakti_uart_reset);
dc->realize = shakti_uart_realize;
device_class_set_props(dc, shakti_uart_properties);
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);

2
hw/char/stm32f2xx_usart.c
View File

@ -228,7 +228,7 @@ static void stm32f2xx_usart_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = stm32f2xx_usart_reset;
device_class_set_legacy_reset(dc, stm32f2xx_usart_reset);
device_class_set_props(dc, stm32f2xx_usart_properties);
dc->realize = stm32f2xx_usart_realize;
}

2
hw/char/xilinx_uartlite.c
View File

@ -234,7 +234,7 @@ static void xilinx_uartlite_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = xilinx_uartlite_reset;
device_class_set_legacy_reset(dc, xilinx_uartlite_reset);
dc->realize = xilinx_uartlite_realize;
device_class_set_props(dc, xilinx_uartlite_properties);
}

2
hw/core/or-irq.c
View File

@ -124,7 +124,7 @@ static void or_irq_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = or_irq_reset;
device_class_set_legacy_reset(dc, or_irq_reset);
device_class_set_props(dc, or_irq_properties);
dc->realize = or_irq_realize;
dc->vmsd = &vmstate_or_irq;

97
hw/core/qdev.c
View File

@ -747,57 +747,6 @@ device_vmstate_if_get_id(VMStateIf *obj)
return qdev_get_dev_path(dev);
}
/**
* device_phases_reset:
* Transition reset method for devices to allow moving
* smoothly from legacy reset method to multi-phases
*/
static void device_phases_reset(DeviceState *dev)
{
ResettableClass *rc = RESETTABLE_GET_CLASS(dev);
if (rc->phases.enter) {
rc->phases.enter(OBJECT(dev), RESET_TYPE_COLD);
}
if (rc->phases.hold) {
rc->phases.hold(OBJECT(dev), RESET_TYPE_COLD);
}
if (rc->phases.exit) {
rc->phases.exit(OBJECT(dev), RESET_TYPE_COLD);
}
}
static void device_transitional_reset(Object *obj)
{
DeviceClass *dc = DEVICE_GET_CLASS(obj);
/*
* This will call either @device_phases_reset (for multi-phases transitioned
* devices) or a device's specific method for not-yet transitioned devices.
* In both case, it does not reset children.
*/
if (dc->reset) {
dc->reset(DEVICE(obj));
}
}
/**
* device_get_transitional_reset:
* check if the device's class is ready for multi-phase
*/
static ResettableTrFunction device_get_transitional_reset(Object *obj)
{
DeviceClass *dc = DEVICE_GET_CLASS(obj);
if (dc->reset != device_phases_reset) {
/*
* dc->reset has been overridden by a subclass,
* the device is not ready for multi phase yet.
*/
return device_transitional_reset;
}
return NULL;
}
static void device_class_init(ObjectClass *class, void *data)
{
DeviceClass *dc = DEVICE_CLASS(class);
@ -819,20 +768,12 @@ static void device_class_init(ObjectClass *class, void *data)
rc->child_foreach = device_reset_child_foreach;
/*
* @device_phases_reset is put as the default reset method below, allowing
* to do the multi-phase transition from base classes to leaf classes. It
* allows a legacy-reset Device class to extend a multi-phases-reset
* Device class for the following reason:
* + If a base class B has been moved to multi-phase, then it does not
* override this default reset method and may have defined phase methods.
* + A child class C (extending class B) which uses
* device_class_set_parent_reset() (or similar means) to override the
* reset method will still work as expected. @device_phases_reset function
* will be registered as the parent reset method and effectively call
* parent reset phases.
* A NULL legacy_reset implies a three-phase reset device. Devices can
* only be reset using three-phase aware mechanisms, but we still support
* for transitional purposes leaf classes which set the old legacy_reset
* method via device_class_set_legacy_reset().
*/
dc->reset = device_phases_reset;
rc->get_transitional_function = device_get_transitional_reset;
dc->legacy_reset = NULL;
object_class_property_add_bool(class, "realized",
device_get_realized, device_set_realized);
@ -844,12 +785,30 @@ static void device_class_init(ObjectClass *class, void *data)
offsetof(DeviceState, parent_bus), NULL, 0);
}
void device_class_set_parent_reset(DeviceClass *dc,
DeviceReset dev_reset,
DeviceReset *parent_reset)
static void do_legacy_reset(Object *obj, ResetType type)
{
*parent_reset = dc->reset;
dc->reset = dev_reset;
DeviceClass *dc = DEVICE_GET_CLASS(obj);
dc->legacy_reset(DEVICE(obj));
}
void device_class_set_legacy_reset(DeviceClass *dc, DeviceReset dev_reset)
{
/*
* A legacy DeviceClass::reset has identical semantics to the
* three-phase "hold" method, with no "enter" or "exit"
* behaviour. Classes that use this legacy function must be leaf
* classes that do not chain up to their parent class reset.
* There is no mechanism for resetting a device that does not
* use the three-phase APIs, so the only place which calls
* the legacy_reset hook is do_legacy_reset().
*/
ResettableClass *rc = RESETTABLE_CLASS(dc);
rc->phases.enter = NULL;
rc->phases.hold = do_legacy_reset;
rc->phases.exit = NULL;
dc->legacy_reset = dev_reset;
}
void device_class_set_parent_realize(DeviceClass *dc,

24
hw/core/resettable.c
View File

@ -93,20 +93,6 @@ static void resettable_child_foreach(ResettableClass *rc, Object *obj,
}
}
/**
* resettable_get_tr_func:
* helper to fetch transitional reset callback if any.
*/
static ResettableTrFunction resettable_get_tr_func(ResettableClass *rc,
Object *obj)
{
ResettableTrFunction tr_func = NULL;
if (rc->get_transitional_function) {
tr_func = rc->get_transitional_function(obj);
}
return tr_func;
}
static void resettable_phase_enter(Object *obj, void *opaque, ResetType type)
{
ResettableClass *rc = RESETTABLE_GET_CLASS(obj);
@ -146,7 +132,7 @@ static void resettable_phase_enter(Object *obj, void *opaque, ResetType type)
if (action_needed) {
trace_resettable_phase_enter_exec(obj, obj_typename, type,
!!rc->phases.enter);
if (rc->phases.enter && !resettable_get_tr_func(rc, obj)) {
if (rc->phases.enter) {
rc->phases.enter(obj, type);
}
s->hold_phase_pending = true;
@ -171,12 +157,8 @@ static void resettable_phase_hold(Object *obj, void *opaque, ResetType type)
/* exec hold phase */
if (s->hold_phase_pending) {
s->hold_phase_pending = false;
ResettableTrFunction tr_func = resettable_get_tr_func(rc, obj);
trace_resettable_phase_hold_exec(obj, obj_typename, !!rc->phases.hold);
if (tr_func) {
trace_resettable_transitional_function(obj, obj_typename);
tr_func(obj);
} else if (rc->phases.hold) {
if (rc->phases.hold) {
rc->phases.hold(obj, type);
}
}
@ -199,7 +181,7 @@ static void resettable_phase_exit(Object *obj, void *opaque, ResetType type)
assert(s->count > 0);
if (--s->count == 0) {
trace_resettable_phase_exit_exec(obj, obj_typename, !!rc->phases.exit);
if (rc->phases.exit && !resettable_get_tr_func(rc, obj)) {
if (rc->phases.exit) {
rc->phases.exit(obj, type);
}
}

2
hw/cxl/switch-mailbox-cci.c
View File

@ -89,7 +89,7 @@ static void cswmbcci_class_init(ObjectClass *oc, void *data)
pc->device_id = 0xa123;
pc->revision = 0;
dc->desc = "CXL Switch Mailbox CCI";
dc->reset = cswmbcci_reset;
device_class_set_legacy_reset(dc, cswmbcci_reset);
device_class_set_props(dc, cxl_switch_cci_props);
}

2
hw/display/artist.c
View File

@ -1491,7 +1491,7 @@ static void artist_class_init(ObjectClass *klass, void *data)
dc->realize = artist_realizefn;
dc->vmsd = &vmstate_artist;
dc->reset = artist_reset;
device_class_set_legacy_reset(dc, artist_reset);
device_class_set_props(dc, artist_properties);
}

2
hw/display/ati.c
View File

@ -1055,7 +1055,7 @@ static void ati_vga_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
dc->reset = ati_vga_reset;
device_class_set_legacy_reset(dc, ati_vga_reset);
device_class_set_props(dc, ati_vga_properties);
dc->hotpluggable = false;
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);

2
hw/display/bcm2835_fb.c
View File

@ -449,7 +449,7 @@ static void bcm2835_fb_class_init(ObjectClass *klass, void *data)
device_class_set_props(dc, bcm2835_fb_props);
dc->realize = bcm2835_fb_realize;
dc->reset = bcm2835_fb_reset;
device_class_set_legacy_reset(dc, bcm2835_fb_reset);
dc->vmsd = &vmstate_bcm2835_fb;
}

2
hw/display/cg3.c
View File

@ -374,7 +374,7 @@ static void cg3_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = cg3_realizefn;
dc->reset = cg3_reset;
device_class_set_legacy_reset(dc, cg3_reset);
dc->vmsd = &vmstate_cg3;
device_class_set_props(dc, cg3_properties);
}

2
hw/display/dpcd.c
View File

@ -145,7 +145,7 @@ static void dpcd_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
dc->reset = dpcd_reset;
device_class_set_legacy_reset(dc, dpcd_reset);
dc->vmsd = &vmstate_dpcd;
}

2
hw/display/exynos4210_fimd.c
View File

@ -1964,7 +1964,7 @@ static void exynos4210_fimd_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->vmsd = &exynos4210_fimd_vmstate;
dc->reset = exynos4210_fimd_reset;
device_class_set_legacy_reset(dc, exynos4210_fimd_reset);
dc->realize = exynos4210_fimd_realize;
device_class_set_props(dc, exynos4210_fimd_properties);
}

2
hw/display/g364fb.c
View File

@ -534,7 +534,7 @@ static void g364fb_sysbus_class_init(ObjectClass *klass, void *data)
dc->realize = g364fb_sysbus_realize;
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
dc->desc = "G364 framebuffer";
dc->reset = g364fb_sysbus_reset;
device_class_set_legacy_reset(dc, g364fb_sysbus_reset);
dc->vmsd = &vmstate_g364fb_sysbus;
device_class_set_props(dc, g364fb_sysbus_properties);
}

2
hw/display/i2c-ddc.c
View File

@ -105,7 +105,7 @@ static void i2c_ddc_class_init(ObjectClass *oc, void *data)
DeviceClass *dc = DEVICE_CLASS(oc);
I2CSlaveClass *isc = I2C_SLAVE_CLASS(oc);
dc->reset = i2c_ddc_reset;
device_class_set_legacy_reset(dc, i2c_ddc_reset);
dc->vmsd = &vmstate_i2c_ddc;
device_class_set_props(dc, i2c_ddc_properties);
isc->event = i2c_ddc_event;

2
hw/display/jazz_led.c
View File

@ -300,7 +300,7 @@ static void jazz_led_class_init(ObjectClass *klass, void *data)
dc->desc = "Jazz LED display",
dc->vmsd = &vmstate_jazz_led;
dc->reset = jazz_led_reset;
device_class_set_legacy_reset(dc, jazz_led_reset);
dc->realize = jazz_led_realize;
}

4
hw/display/macfb.c
View File

@ -802,7 +802,7 @@ static void macfb_sysbus_class_init(ObjectClass *klass, void *data)
dc->realize = macfb_sysbus_realize;
dc->desc = "SysBus Macintosh framebuffer";
dc->reset = macfb_sysbus_reset;
device_class_set_legacy_reset(dc, macfb_sysbus_reset);
dc->vmsd = &vmstate_macfb_sysbus;
device_class_set_props(dc, macfb_sysbus_properties);
}
@ -817,7 +817,7 @@ static void macfb_nubus_class_init(ObjectClass *klass, void *data)
device_class_set_parent_unrealize(dc, macfb_nubus_unrealize,
&ndc->parent_unrealize);
dc->desc = "Nubus Macintosh framebuffer";
dc->reset = macfb_nubus_reset;
device_class_set_legacy_reset(dc, macfb_nubus_reset);
dc->vmsd = &vmstate_macfb_nubus;
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
device_class_set_props(dc, macfb_nubus_properties);

2
hw/display/qxl.c
View File

@ -2486,7 +2486,7 @@ static void qxl_pci_class_init(ObjectClass *klass, void *data)
k->vendor_id = REDHAT_PCI_VENDOR_ID;
k->device_id = QXL_DEVICE_ID_STABLE;
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
dc->reset = qxl_reset_handler;
device_class_set_legacy_reset(dc, qxl_reset_handler);
dc->vmsd = &qxl_vmstate;
device_class_set_props(dc, qxl_properties);
}

2
hw/display/sii9022.c
View File

@ -175,7 +175,7 @@ static void sii9022_class_init(ObjectClass *klass, void *data)
k->event = sii9022_event;
k->recv = sii9022_rx;
k->send = sii9022_tx;
dc->reset = sii9022_reset;
device_class_set_legacy_reset(dc, sii9022_reset);
dc->realize = sii9022_realize;
dc->vmsd = &vmstate_sii9022;
}

4
hw/display/sm501.c
View File

@ -2086,7 +2086,7 @@ static void sm501_sysbus_class_init(ObjectClass *klass, void *data)
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
dc->desc = "SM501 Multimedia Companion";
device_class_set_props(dc, sm501_sysbus_properties);
dc->reset = sm501_reset_sysbus;
device_class_set_legacy_reset(dc, sm501_reset_sysbus);
dc->vmsd = &vmstate_sm501_sysbus;
}
@ -2181,7 +2181,7 @@ static void sm501_pci_class_init(ObjectClass *klass, void *data)
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
dc->desc = "SM501 Display Controller";
device_class_set_props(dc, sm501_pci_properties);
dc->reset = sm501_reset_pci;
device_class_set_legacy_reset(dc, sm501_reset_pci);
dc->hotpluggable = false;
dc->vmsd = &vmstate_sm501_pci;
}

2
hw/display/tcx.c
View File

@ -892,7 +892,7 @@ static void tcx_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = tcx_realizefn;
dc->reset = tcx_reset;
device_class_set_legacy_reset(dc, tcx_reset);
dc->vmsd = &vmstate_tcx;
device_class_set_props(dc, tcx_properties);
}

2
hw/display/vga-isa.c
View File

@ -98,7 +98,7 @@ static void vga_isa_class_initfn(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = vga_isa_realizefn;
dc->reset = vga_isa_reset;
device_class_set_legacy_reset(dc, vga_isa_reset);
dc->vmsd = &vmstate_vga_common;
device_class_set_props(dc, vga_isa_properties);
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);

2
hw/display/vga-mmio.c
View File

@ -122,7 +122,7 @@ static void vga_mmio_class_initfn(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = vga_mmio_realizefn;
dc->reset = vga_mmio_reset;
device_class_set_legacy_reset(dc, vga_mmio_reset);
dc->vmsd = &vmstate_vga_common;
device_class_set_props(dc, vga_mmio_properties);
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);

2
hw/display/vga-pci.c
View File

@ -403,7 +403,7 @@ static void secondary_class_init(ObjectClass *klass, void *data)
k->exit = pci_secondary_vga_exit;
k->class_id = PCI_CLASS_DISPLAY_OTHER;
device_class_set_props(dc, secondary_pci_properties);
dc->reset = pci_secondary_vga_reset;
device_class_set_legacy_reset(dc, pci_secondary_vga_reset);
}
static const TypeInfo vga_info = {

2
hw/display/vmware_vga.c
View File

@ -1352,7 +1352,7 @@ static void vmsvga_class_init(ObjectClass *klass, void *data)
k->class_id = PCI_CLASS_DISPLAY_VGA;
k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
k->subsystem_id = SVGA_PCI_DEVICE_ID;
dc->reset = vmsvga_reset;
device_class_set_legacy_reset(dc, vmsvga_reset);
dc->vmsd = &vmstate_vmware_vga;
device_class_set_props(dc, vga_vmware_properties);
dc->hotpluggable = false;

2
hw/display/xlnx_dp.c
View File

@ -1398,7 +1398,7 @@ static void xlnx_dp_class_init(ObjectClass *oc, void *data)
dc->realize = xlnx_dp_realize;
dc->vmsd = &vmstate_dp;
dc->reset = xlnx_dp_reset;
device_class_set_legacy_reset(dc, xlnx_dp_reset);
device_class_set_props(dc, xlnx_dp_device_properties);
}

2
hw/dma/bcm2835_dma.c
View File

@ -390,7 +390,7 @@ static void bcm2835_dma_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = bcm2835_dma_realize;
dc->reset = bcm2835_dma_reset;
device_class_set_legacy_reset(dc, bcm2835_dma_reset);
dc->vmsd = &vmstate_bcm2835_dma;
}

2
hw/dma/i8257.c
View File

@ -599,7 +599,7 @@ static void i8257_class_init(ObjectClass *klass, void *data)
IsaDmaClass *idc = ISADMA_CLASS(klass);
dc->realize = i8257_realize;
dc->reset = i8257_reset;
device_class_set_legacy_reset(dc, i8257_reset);
dc->vmsd = &vmstate_i8257;
device_class_set_props(dc, i8257_properties);

2
hw/dma/pl080.c
View File

@ -421,7 +421,7 @@ static void pl080_class_init(ObjectClass *oc, void *data)
dc->vmsd = &vmstate_pl080;
dc->realize = pl080_realize;
device_class_set_props(dc, pl080_properties);
dc->reset = pl080_reset;
device_class_set_legacy_reset(dc, pl080_reset);
}
static const TypeInfo pl080_info = {

2
hw/dma/pl330.c
View File

@ -1678,7 +1678,7 @@ static void pl330_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = pl330_realize;
dc->reset = pl330_reset;
device_class_set_legacy_reset(dc, pl330_reset);
device_class_set_props(dc, pl330_properties);
dc->vmsd = &vmstate_pl330;
}

2
hw/dma/rc4030.c
View File

@ -707,7 +707,7 @@ static void rc4030_class_init(ObjectClass *klass, void *class_data)
dc->realize = rc4030_realize;
dc->unrealize = rc4030_unrealize;
dc->reset = rc4030_reset;
device_class_set_legacy_reset(dc, rc4030_reset);
dc->vmsd = &vmstate_rc4030;
}

2
hw/dma/sparc32_dma.c
View File

@ -278,7 +278,7 @@ static void sparc32_dma_device_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = sparc32_dma_device_reset;
device_class_set_legacy_reset(dc, sparc32_dma_device_reset);
dc->vmsd = &vmstate_sparc32_dma_device;
}

2
hw/dma/xilinx_axidma.c
View File

@ -627,7 +627,7 @@ static void axidma_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = xilinx_axidma_realize;
dc->reset = xilinx_axidma_reset;
device_class_set_legacy_reset(dc, xilinx_axidma_reset);
device_class_set_props(dc, axidma_properties);
}

2
hw/dma/xlnx-zdma.c
View File

@ -821,7 +821,7 @@ static void zdma_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = zdma_reset;
device_class_set_legacy_reset(dc, zdma_reset);
dc->realize = zdma_realize;
device_class_set_props(dc, zdma_props);
dc->vmsd = &vmstate_zdma;

2
hw/dma/xlnx-zynq-devcfg.c
View File

@ -384,7 +384,7 @@ static void xlnx_zynq_devcfg_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = xlnx_zynq_devcfg_reset;
device_class_set_legacy_reset(dc, xlnx_zynq_devcfg_reset);
dc->vmsd = &vmstate_xlnx_zynq_devcfg;
}

2
hw/dma/xlnx_csu_dma.c
View File

@ -719,7 +719,7 @@ static void xlnx_csu_dma_class_init(ObjectClass *klass, void *data)
StreamSinkClass *ssc = STREAM_SINK_CLASS(klass);
XlnxCSUDMAClass *xcdc = XLNX_CSU_DMA_CLASS(klass);
dc->reset = xlnx_csu_dma_reset;
device_class_set_legacy_reset(dc, xlnx_csu_dma_reset);
dc->realize = xlnx_csu_dma_realize;
dc->vmsd = &vmstate_xlnx_csu_dma;
device_class_set_props(dc, xlnx_csu_dma_properties);

2
hw/dma/xlnx_dpdma.c
View File

@ -598,7 +598,7 @@ static void xlnx_dpdma_class_init(ObjectClass *oc, void *data)
DeviceClass *dc = DEVICE_CLASS(oc);
dc->vmsd = &vmstate_xlnx_dpdma;
dc->reset = xlnx_dpdma_reset;
device_class_set_legacy_reset(dc, xlnx_dpdma_reset);
}
static const TypeInfo xlnx_dpdma_info = {

2
hw/fsi/aspeed_apb2opb.c
View File

@ -326,7 +326,7 @@ static void fsi_aspeed_apb2opb_class_init(ObjectClass *klass, void *data)
dc->desc = "ASPEED APB2OPB Bridge";
dc->realize = fsi_aspeed_apb2opb_realize;
dc->reset = fsi_aspeed_apb2opb_reset;
device_class_set_legacy_reset(dc, fsi_aspeed_apb2opb_reset);
}
static const TypeInfo aspeed_apb2opb_info = {

2
hw/fsi/fsi-master.c
View File

@ -151,7 +151,7 @@ static void fsi_master_class_init(ObjectClass *klass, void *data)
dc->bus_type = TYPE_OP_BUS;
dc->desc = "FSI Master";
dc->realize = fsi_master_realize;
dc->reset = fsi_master_reset;
device_class_set_legacy_reset(dc, fsi_master_reset);
}
static const TypeInfo fsi_master_info = {

2
hw/fsi/fsi.c
View File

@ -82,7 +82,7 @@ static void fsi_slave_class_init(ObjectClass *klass, void *data)
dc->bus_type = TYPE_FSI_BUS;
dc->desc = "FSI Slave";
dc->reset = fsi_slave_reset;
device_class_set_legacy_reset(dc, fsi_slave_reset);
}
static const TypeInfo fsi_slave_info = {

2
hw/fsi/lbus.c
View File

@ -97,7 +97,7 @@ static void fsi_scratchpad_class_init(ObjectClass *klass, void *data)
dc->bus_type = TYPE_FSI_LBUS;
dc->realize = fsi_scratchpad_realize;
dc->reset = fsi_scratchpad_reset;
device_class_set_legacy_reset(dc, fsi_scratchpad_reset);
}
static const TypeInfo fsi_scratchpad_info = {

2
hw/gpio/aspeed_gpio.c
View File

@ -1116,7 +1116,7 @@ static void aspeed_gpio_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = aspeed_gpio_realize;
dc->reset = aspeed_gpio_reset;
device_class_set_legacy_reset(dc, aspeed_gpio_reset);
dc->desc = "Aspeed GPIO Controller";
dc->vmsd = &vmstate_aspeed_gpio;
}

2
hw/gpio/bcm2835_gpio.c
View File

@ -325,7 +325,7 @@ static void bcm2835_gpio_class_init(ObjectClass *klass, void *data)
dc->vmsd = &vmstate_bcm2835_gpio;
dc->realize = &bcm2835_gpio_realize;
dc->reset = &bcm2835_gpio_reset;
device_class_set_legacy_reset(dc, bcm2835_gpio_reset);
}
static const TypeInfo bcm2835_gpio_info = {

2
hw/gpio/bcm2838_gpio.c
View File

@ -371,7 +371,7 @@ static void bcm2838_gpio_class_init(ObjectClass *klass, void *data)
dc->vmsd = &vmstate_bcm2838_gpio;
dc->realize = &bcm2838_gpio_realize;
dc->reset = &bcm2838_gpio_reset;
device_class_set_legacy_reset(dc, bcm2838_gpio_reset);
}
static const TypeInfo bcm2838_gpio_info = {

2
hw/gpio/gpio_key.c
View File

@ -91,7 +91,7 @@ static void gpio_key_class_init(ObjectClass *klass, void *data)
dc->realize = gpio_key_realize;
dc->vmsd = &vmstate_gpio_key;
dc->reset = &gpio_key_reset;
device_class_set_legacy_reset(dc, gpio_key_reset);
}
static const TypeInfo gpio_key_info = {

2
hw/gpio/imx_gpio.c
View File

@ -333,7 +333,7 @@ static void imx_gpio_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = imx_gpio_realize;
dc->reset = imx_gpio_reset;
device_class_set_legacy_reset(dc, imx_gpio_reset);
device_class_set_props(dc, imx_gpio_properties);
dc->vmsd = &vmstate_imx_gpio;
dc->desc = "i.MX GPIO controller";

2
hw/gpio/max7310.c
View File

@ -198,7 +198,7 @@ static void max7310_class_init(ObjectClass *klass, void *data)
k->event = max7310_event;
k->recv = max7310_rx;
k->send = max7310_tx;
dc->reset = max7310_reset;
device_class_set_legacy_reset(dc, max7310_reset);
dc->vmsd = &vmstate_max7310;
}

2
hw/gpio/mpc8xxx.c
View File

@ -205,7 +205,7 @@ static void mpc8xxx_gpio_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->vmsd = &vmstate_mpc8xxx_gpio;
dc->reset = mpc8xxx_gpio_reset;
device_class_set_legacy_reset(dc, mpc8xxx_gpio_reset);
}
static const TypeInfo mpc8xxx_gpio_info = {

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