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hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG definition 

The current MCHP_PFSOC_MMUART_REG_SIZE definition represent the
size occupied by all the registers. However all registers are
32-bit wide, and the MemoryRegionOps handlers are restricted to
32-bit:

  static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
      .read = mchp_pfsoc_mmuart_read,
      .write = mchp_pfsoc_mmuart_write,
      .impl = {
          .min_access_size = 4,
          .max_access_size = 4,
      },

Avoid being triskaidekaphobic, simplify by using the number of
registers.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210925133407.1259392-2-f4bug@amsat.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Philippe Mathieu-Daudé 2021-09-25 15:34:05 +02:00 committed by Alistair Francis
parent 6a03349007
commit 284a66a8f6
2 changed files with 10 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
hw/char/mchp_pfsoc_mmuart.c
View File

@ -29,13 +29,14 @@ static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size)
{ {
MchpPfSoCMMUartState *s = opaque; MchpPfSoCMMUartState *s = opaque;
if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) { addr >>= 2;
if (addr >= MCHP_PFSOC_MMUART_REG_COUNT) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n", qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n",
__func__, addr); __func__, addr << 2);
return 0; return 0;
} }
return s->reg[addr / sizeof(uint32_t)]; return s->reg[addr];
} }
static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr, static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr,
@ -44,13 +45,14 @@ static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr,
MchpPfSoCMMUartState *s = opaque; MchpPfSoCMMUartState *s = opaque;
uint32_t val32 = (uint32_t)value; uint32_t val32 = (uint32_t)value;
if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) { addr >>= 2;
if (addr >= MCHP_PFSOC_MMUART_REG_COUNT) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
" v=0x%x\n", __func__, addr, val32); " v=0x%x\n", __func__, addr << 2, val32);
return; return;
} }
s->reg[addr / sizeof(uint32_t)] = val32; s->reg[addr] = val32;
} }
static const MemoryRegionOps mchp_pfsoc_mmuart_ops = { static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {

4
include/hw/char/mchp_pfsoc_mmuart.h
View File

@ -30,7 +30,7 @@
#include "hw/char/serial.h" #include "hw/char/serial.h"
#define MCHP_PFSOC_MMUART_REG_SIZE 52 #define MCHP_PFSOC_MMUART_REG_COUNT 13
typedef struct MchpPfSoCMMUartState { typedef struct MchpPfSoCMMUartState {
MemoryRegion iomem; MemoryRegion iomem;
@ -39,7 +39,7 @@ typedef struct MchpPfSoCMMUartState {
SerialMM *serial; SerialMM *serial;
uint32_t reg[MCHP_PFSOC_MMUART_REG_SIZE / sizeof(uint32_t)]; uint32_t reg[MCHP_PFSOC_MMUART_REG_COUNT];
} MchpPfSoCMMUartState; } MchpPfSoCMMUartState;
/** /**