mirror of https://github.com/xemu-project/xemu.git
target/hppa: Use delay_excp for conditional traps
Reviewed-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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806030074b
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269ca0a9cc
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@ -1,6 +1,5 @@
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DEF_HELPER_2(excp, noreturn, env, int)
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DEF_HELPER_FLAGS_2(tsv, TCG_CALL_NO_WG, void, env, tl)
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DEF_HELPER_FLAGS_2(tcond, TCG_CALL_NO_WG, void, env, tl)
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DEF_HELPER_FLAGS_3(stby_b, TCG_CALL_NO_WG, void, env, tl, tl)
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DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tl)
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@ -134,13 +134,13 @@ void hppa_cpu_do_interrupt(CPUState *cs)
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switch (i) {
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case EXCP_ILL:
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case EXCP_BREAK:
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case EXCP_COND:
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case EXCP_PRIV_REG:
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case EXCP_PRIV_OPR:
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/* IIR set via translate.c. */
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break;
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case EXCP_OVERFLOW:
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case EXCP_COND:
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case EXCP_ASSIST:
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case EXCP_DTLB_MISS:
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case EXCP_NA_ITLB_MISS:
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@ -49,13 +49,6 @@ void HELPER(tsv)(CPUHPPAState *env, target_ulong cond)
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}
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}
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void HELPER(tcond)(CPUHPPAState *env, target_ulong cond)
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{
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if (unlikely(cond)) {
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hppa_dynamic_excp(env, EXCP_COND, GETPC());
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}
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}
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static void atomic_store_mask32(CPUHPPAState *env, target_ulong addr,
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uint32_t val, uint32_t mask, uintptr_t ra)
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{
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@ -1117,6 +1117,25 @@ static TCGv_i64 do_sub_sv(DisasContext *ctx, TCGv_i64 res,
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return sv;
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}
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static void gen_tc(DisasContext *ctx, DisasCond *cond)
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{
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DisasDelayException *e;
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switch (cond->c) {
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case TCG_COND_NEVER:
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break;
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case TCG_COND_ALWAYS:
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gen_excp_iir(ctx, EXCP_COND);
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break;
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default:
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e = delay_excp(ctx, EXCP_COND);
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tcg_gen_brcond_i64(cond->c, cond->a0, cond->a1, e->lab);
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/* In the non-trap path, the condition is known false. */
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*cond = cond_make_f();
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break;
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}
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}
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static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 orig_in1,
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TCGv_i64 in2, unsigned shift, bool is_l,
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bool is_tsv, bool is_tc, bool is_c, unsigned cf, bool d)
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@ -1175,9 +1194,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 orig_in1,
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/* Emit any conditional trap before any writeback. */
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cond = do_cond(ctx, cf, d, dest, uv, sv);
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if (is_tc) {
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tmp = tcg_temp_new_i64();
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tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1);
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gen_helper_tcond(tcg_env, tmp);
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gen_tc(ctx, &cond);
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}
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/* Write back the result. */
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@ -1196,6 +1213,10 @@ static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_d_sh *a,
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{
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TCGv_i64 tcg_r1, tcg_r2;
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if (unlikely(is_tc && a->cf == 1)) {
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/* Unconditional trap on condition. */
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return gen_excp_iir(ctx, EXCP_COND);
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}
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if (a->cf) {
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nullify_over(ctx);
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}
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@ -1211,6 +1232,10 @@ static bool do_add_imm(DisasContext *ctx, arg_rri_cf *a,
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{
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TCGv_i64 tcg_im, tcg_r2;
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if (unlikely(is_tc && a->cf == 1)) {
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/* Unconditional trap on condition. */
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return gen_excp_iir(ctx, EXCP_COND);
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}
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if (a->cf) {
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nullify_over(ctx);
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}
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@ -1225,7 +1250,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
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TCGv_i64 in2, bool is_tsv, bool is_b,
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bool is_tc, unsigned cf, bool d)
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{
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TCGv_i64 dest, sv, cb, cb_msb, tmp;
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TCGv_i64 dest, sv, cb, cb_msb;
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unsigned c = cf >> 1;
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DisasCond cond;
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@ -1273,9 +1298,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
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/* Emit any conditional trap before any writeback. */
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if (is_tc) {
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tmp = tcg_temp_new_i64();
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tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1);
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gen_helper_tcond(tcg_env, tmp);
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gen_tc(ctx, &cond);
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}
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/* Write back the result. */
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@ -1441,9 +1464,7 @@ static void do_unit_addsub(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
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}
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if (is_tc) {
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TCGv_i64 tmp = tcg_temp_new_i64();
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tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1);
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gen_helper_tcond(tcg_env, tmp);
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gen_tc(ctx, &cond);
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}
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save_gpr(ctx, rt, dest);
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