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target/mips: Add CP0 BadInstrX register 

Add CP0 BadInstrX register. This register will be used in nanoMIPS.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
This commit is contained in:
Stefan Markovic 2018-08-02 16:15:53 +02:00 committed by Aleksandar Markovic
parent 0413d7a55a
commit 25beba9bf7
3 changed files with 25 additions and 3 deletions
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1
target/mips/cpu.h
View File

@ -323,6 +323,7 @@ struct CPUMIPSState {
target_ulong CP0_BadVAddr; target_ulong CP0_BadVAddr;
uint32_t CP0_BadInstr; uint32_t CP0_BadInstr;
uint32_t CP0_BadInstrP; uint32_t CP0_BadInstrP;
uint32_t CP0_BadInstrX;
int32_t CP0_Count; int32_t CP0_Count;
target_ulong CP0_EntryHi; target_ulong CP0_EntryHi;
#define CP0EnHi_EHINV 10 #define CP0EnHi_EHINV 10

5
target/mips/machine.c
View File

@ -212,8 +212,8 @@ const VMStateDescription vmstate_tlb = {
const VMStateDescription vmstate_mips_cpu = { const VMStateDescription vmstate_mips_cpu = {
.name = "cpu", .name = "cpu",
.version_id = 10, .version_id = 11,
.minimum_version_id = 10, .minimum_version_id = 11,
.post_load = cpu_post_load, .post_load = cpu_post_load,
.fields = (VMStateField[]) { .fields = (VMStateField[]) {
/* Active TC */ /* Active TC */
@ -266,6 +266,7 @@ const VMStateDescription vmstate_mips_cpu = {
VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU), VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU),
VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU), VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU),
VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU), VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
VMSTATE_INT32(env.CP0_Count, MIPSCPU), VMSTATE_INT32(env.CP0_Count, MIPSCPU),
VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU), VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
VMSTATE_INT32(env.CP0_Compare, MIPSCPU), VMSTATE_INT32(env.CP0_Compare, MIPSCPU),

22
target/mips/translate.c
View File

@ -5328,7 +5328,13 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
rn = "BadInstrP"; rn = "BadInstrP";
break; break;
default: case 3:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
tcg_gen_andi_tl(arg, arg, ~0xffff);
rn = "BadInstrX";
break;
default:
goto cp0_unimplemented; goto cp0_unimplemented;
} }
break; break;
@ -6019,6 +6025,10 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* ignored */ /* ignored */
rn = "BadInstrP"; rn = "BadInstrP";
break; break;
case 3:
/* ignored */
rn = "BadInstrX";
break;
default: default:
goto cp0_unimplemented; goto cp0_unimplemented;
} }
@ -6724,6 +6734,12 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
rn = "BadInstrP"; rn = "BadInstrP";
break; break;
case 3:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
tcg_gen_andi_tl(arg, arg, ~0xffff);
rn = "BadInstrX";
break;
default: default:
goto cp0_unimplemented; goto cp0_unimplemented;
} }
@ -7398,6 +7414,10 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* ignored */ /* ignored */
rn = "BadInstrP"; rn = "BadInstrP";
break; break;
case 3:
/* ignored */
rn = "BadInstrX";
break;
default: default:
goto cp0_unimplemented; goto cp0_unimplemented;
} }