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pc,virtio: last minute bugfixes 

Two last minute bugfixes. They are both designed to prevent
 compatibility headaches down the road.
 
 Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging

pc,virtio: last minute bugfixes

Two last minute bugfixes. They are both designed to prevent
compatibility headaches down the road.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

# gpg: Signature made Tue 06 Apr 2021 12:13:07 BST
# gpg:                using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg:                issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17  0970 C350 3912 AFBE 8E67
#      Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA  8A0D 281F 0DB8 D28D 5469

* remotes/mst/tags/for_upstream:
  virtio-pci: compat page aligned ATS
  x86: rename oem-id and oem-table-id properties

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2021-04-06 13:22:51 +01:00
parent 109918d24a d83f46d189
commit 259e909790
8 changed files with 24 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
hw/arm/virt.c
View File

@ -2670,19 +2670,19 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
"Set on/off to enable/disable " "Set on/off to enable/disable "
"ITS instantiation"); "ITS instantiation");
object_class_property_add_str(oc, "oem-id", object_class_property_add_str(oc, "x-oem-id",
virt_get_oem_id, virt_get_oem_id,
virt_set_oem_id); virt_set_oem_id);
object_class_property_set_description(oc, "oem-id", object_class_property_set_description(oc, "x-oem-id",
"Override the default value of field OEMID " "Override the default value of field OEMID "
"in ACPI table header." "in ACPI table header."
"The string may be up to 6 bytes in size"); "The string may be up to 6 bytes in size");
object_class_property_add_str(oc, "oem-table-id", object_class_property_add_str(oc, "x-oem-table-id",
virt_get_oem_table_id, virt_get_oem_table_id,
virt_set_oem_table_id); virt_set_oem_table_id);
object_class_property_set_description(oc, "oem-table-id", object_class_property_set_description(oc, "x-oem-table-id",
"Override the default value of field OEM Table ID " "Override the default value of field OEM Table ID "
"in ACPI table header." "in ACPI table header."
"The string may be up to 8 bytes in size"); "The string may be up to 8 bytes in size");

1
hw/core/machine.c
View File

@ -53,6 +53,7 @@ GlobalProperty hw_compat_5_1[] = {
{ "nvme", "use-intel-id", "on"}, { "nvme", "use-intel-id", "on"},
{ "pvpanic", "events", "1"}, /* PVPANIC_PANICKED */ { "pvpanic", "events", "1"}, /* PVPANIC_PANICKED */
{ "pl011", "migrate-clk", "off" }, { "pl011", "migrate-clk", "off" },
{ "virtio-pci", "x-ats-page-aligned", "off"},
}; };
const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1); const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1);

10
hw/pci/pcie.c
View File

@ -963,16 +963,18 @@ void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num)
pci_set_quad(dev->config + offset + pci_dsn_cap, ser_num); pci_set_quad(dev->config + offset + pci_dsn_cap, ser_num);
} }
void pcie_ats_init(PCIDevice *dev, uint16_t offset) void pcie_ats_init(PCIDevice *dev, uint16_t offset, bool aligned)
{ {
pcie_add_capability(dev, PCI_EXT_CAP_ID_ATS, 0x1, pcie_add_capability(dev, PCI_EXT_CAP_ID_ATS, 0x1,
offset, PCI_EXT_CAP_ATS_SIZEOF); offset, PCI_EXT_CAP_ATS_SIZEOF);
dev->exp.ats_cap = offset; dev->exp.ats_cap = offset;
/* Invalidate Queue Depth 0, Page Aligned Request 1 */ /* Invalidate Queue Depth 0 */
pci_set_word(dev->config + offset + PCI_ATS_CAP, if (aligned) {
PCI_ATS_CAP_PAGE_ALIGNED); pci_set_word(dev->config + offset + PCI_ATS_CAP,
PCI_ATS_CAP_PAGE_ALIGNED);
}
/* STU 0, Disabled by default */ /* STU 0, Disabled by default */
pci_set_word(dev->config + offset + PCI_ATS_CTRL, 0); pci_set_word(dev->config + offset + PCI_ATS_CTRL, 0);

5
hw/virtio/virtio-pci.c
View File

@ -1856,7 +1856,8 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
} }
if (proxy->flags & VIRTIO_PCI_FLAG_ATS) { if (proxy->flags & VIRTIO_PCI_FLAG_ATS) {
pcie_ats_init(pci_dev, last_pcie_cap_offset); pcie_ats_init(pci_dev, last_pcie_cap_offset,
proxy->flags & VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED);
last_pcie_cap_offset += PCI_EXT_CAP_ATS_SIZEOF; last_pcie_cap_offset += PCI_EXT_CAP_ATS_SIZEOF;
} }
@ -1933,6 +1934,8 @@ static Property virtio_pci_properties[] = {
ignore_backend_features, false), ignore_backend_features, false),
DEFINE_PROP_BIT("ats", VirtIOPCIProxy, flags, DEFINE_PROP_BIT("ats", VirtIOPCIProxy, flags,
VIRTIO_PCI_FLAG_ATS_BIT, false), VIRTIO_PCI_FLAG_ATS_BIT, false),
DEFINE_PROP_BIT("x-ats-page-aligned", VirtIOPCIProxy, flags,
VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED_BIT, true),
DEFINE_PROP_BIT("x-pcie-deverr-init", VirtIOPCIProxy, flags, DEFINE_PROP_BIT("x-pcie-deverr-init", VirtIOPCIProxy, flags,
VIRTIO_PCI_FLAG_INIT_DEVERR_BIT, true), VIRTIO_PCI_FLAG_INIT_DEVERR_BIT, true),
DEFINE_PROP_BIT("x-pcie-lnkctl-init", VirtIOPCIProxy, flags, DEFINE_PROP_BIT("x-pcie-lnkctl-init", VirtIOPCIProxy, flags,

5
hw/virtio/virtio-pci.h
View File

@ -42,6 +42,7 @@ enum {
VIRTIO_PCI_FLAG_INIT_PM_BIT, VIRTIO_PCI_FLAG_INIT_PM_BIT,
VIRTIO_PCI_FLAG_INIT_FLR_BIT, VIRTIO_PCI_FLAG_INIT_FLR_BIT,
VIRTIO_PCI_FLAG_AER_BIT, VIRTIO_PCI_FLAG_AER_BIT,
VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED_BIT,
}; };
/* Need to activate work-arounds for buggy guests at vmstate load. */ /* Need to activate work-arounds for buggy guests at vmstate load. */
@ -84,6 +85,10 @@ enum {
/* Advanced Error Reporting capability */ /* Advanced Error Reporting capability */
#define VIRTIO_PCI_FLAG_AER (1 << VIRTIO_PCI_FLAG_AER_BIT) #define VIRTIO_PCI_FLAG_AER (1 << VIRTIO_PCI_FLAG_AER_BIT)
/* Page Aligned Address space Translation Service */
#define VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED \
(1 << VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED_BIT)
typedef struct { typedef struct {
MSIMessage msg; MSIMessage msg;
int virq; int virq;

4
include/hw/i386/x86.h
View File

@ -78,8 +78,8 @@ struct X86MachineState {
#define X86_MACHINE_SMM "smm" #define X86_MACHINE_SMM "smm"
#define X86_MACHINE_ACPI "acpi" #define X86_MACHINE_ACPI "acpi"
#define X86_MACHINE_OEM_ID "oem-id" #define X86_MACHINE_OEM_ID "x-oem-id"
#define X86_MACHINE_OEM_TABLE_ID "oem-table-id" #define X86_MACHINE_OEM_TABLE_ID "x-oem-table-id"
#define TYPE_X86_MACHINE MACHINE_TYPE_NAME("x86") #define TYPE_X86_MACHINE MACHINE_TYPE_NAME("x86")
OBJECT_DECLARE_TYPE(X86MachineState, X86MachineClass, X86_MACHINE) OBJECT_DECLARE_TYPE(X86MachineState, X86MachineClass, X86_MACHINE)

2
include/hw/pci/pcie.h
View File

@ -137,7 +137,7 @@ void pcie_acs_reset(PCIDevice *dev);
void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn); void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn);
void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num); void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num);
void pcie_ats_init(PCIDevice *dev, uint16_t offset); void pcie_ats_init(PCIDevice *dev, uint16_t offset, bool aligned);
void pcie_cap_slot_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, void pcie_cap_slot_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
Error **errp); Error **errp);

2
tests/qtest/bios-tables-test.c
View File

@ -73,7 +73,7 @@
#define OEM_ID "TEST" #define OEM_ID "TEST"
#define OEM_TABLE_ID "OEM" #define OEM_TABLE_ID "OEM"
#define OEM_TEST_ARGS "-machine oem-id="OEM_ID",oem-table-id="OEM_TABLE_ID #define OEM_TEST_ARGS "-machine x-oem-id="OEM_ID",x-oem-table-id="OEM_TABLE_ID
typedef struct { typedef struct {
bool tcg_only; bool tcg_only;