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target-arm: Use setcond and movcond for csel 

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-id: 1441909103-24666-5-git-send-email-rth@twiddle.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2015-09-14 14:39:47 +01:00 committed by Peter Maydell
parent 9305eac09e
commit 259cb68491
1 changed files with 49 additions and 36 deletions
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85
target-arm/translate-a64.c
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@ -167,6 +167,31 @@ void gen_a64_set_pc_im(uint64_t val)
tcg_gen_movi_i64(cpu_pc, val); tcg_gen_movi_i64(cpu_pc, val);
} }
typedef struct DisasCompare64 {
TCGCond cond;
TCGv_i64 value;
} DisasCompare64;
static void a64_test_cc(DisasCompare64 *c64, int cc)
{
DisasCompare c32;
arm_test_cc(&c32, cc);
/* Sign-extend the 32-bit value so that the GE/LT comparisons work
* properly. The NE/EQ comparisons are also fine with this choice. */
c64->cond = c32.cond;
c64->value = tcg_temp_new_i64();
tcg_gen_ext_i32_i64(c64->value, c32.value);
arm_free_cc(&c32);
}
static void a64_free_cc(DisasCompare64 *c64)
{
tcg_temp_free_i64(c64->value);
}
static void gen_exception_internal(int excp) static void gen_exception_internal(int excp)
{ {
TCGv_i32 tcg_excp = tcg_const_i32(excp); TCGv_i32 tcg_excp = tcg_const_i32(excp);
@ -3607,7 +3632,8 @@ static void disas_cc(DisasContext *s, uint32_t insn)
static void disas_cond_select(DisasContext *s, uint32_t insn) static void disas_cond_select(DisasContext *s, uint32_t insn)
{ {
unsigned int sf, else_inv, rm, cond, else_inc, rn, rd; unsigned int sf, else_inv, rm, cond, else_inc, rn, rd;
TCGv_i64 tcg_rd, tcg_src; TCGv_i64 tcg_rd, zero;
DisasCompare64 c;
if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) { if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) {
/* S == 1 or op2<1> == 1 */ /* S == 1 or op2<1> == 1 */
@ -3622,48 +3648,35 @@ static void disas_cond_select(DisasContext *s, uint32_t insn)
rn = extract32(insn, 5, 5); rn = extract32(insn, 5, 5);
rd = extract32(insn, 0, 5); rd = extract32(insn, 0, 5);
if (rd == 31) {
/* silly no-op write; until we use movcond we must special-case
* this to avoid a dead temporary across basic blocks.
*/
return;
}
tcg_rd = cpu_reg(s, rd); tcg_rd = cpu_reg(s, rd);
if (cond >= 0x0e) { /* condition "always" */ a64_test_cc(&c, cond);
tcg_src = read_cpu_reg(s, rn, sf); zero = tcg_const_i64(0);
tcg_gen_mov_i64(tcg_rd, tcg_src);
if (rn == 31 && rm == 31 && (else_inc ^ else_inv)) {
/* CSET & CSETM. */
tcg_gen_setcond_i64(tcg_invert_cond(c.cond), tcg_rd, c.value, zero);
if (else_inv) {
tcg_gen_neg_i64(tcg_rd, tcg_rd);
}
} else { } else {
/* OPTME: we could use movcond here, at the cost of duplicating TCGv_i64 t_true = cpu_reg(s, rn);
* a lot of the arm_gen_test_cc() logic. TCGv_i64 t_false = read_cpu_reg(s, rm, 1);
*/
TCGLabel *label_match = gen_new_label();
TCGLabel *label_continue = gen_new_label();
arm_gen_test_cc(cond, label_match);
/* nomatch: */
tcg_src = cpu_reg(s, rm);
if (else_inv && else_inc) { if (else_inv && else_inc) {
tcg_gen_neg_i64(tcg_rd, tcg_src); tcg_gen_neg_i64(t_false, t_false);
} else if (else_inv) { } else if (else_inv) {
tcg_gen_not_i64(tcg_rd, tcg_src); tcg_gen_not_i64(t_false, t_false);
} else if (else_inc) { } else if (else_inc) {
tcg_gen_addi_i64(tcg_rd, tcg_src, 1); tcg_gen_addi_i64(t_false, t_false, 1);
} else {
tcg_gen_mov_i64(tcg_rd, tcg_src);
} }
if (!sf) { tcg_gen_movcond_i64(c.cond, tcg_rd, c.value, zero, t_true, t_false);
tcg_gen_ext32u_i64(tcg_rd, tcg_rd); }
}
tcg_gen_br(label_continue); tcg_temp_free_i64(zero);
/* match: */ a64_free_cc(&c);
gen_set_label(label_match);
tcg_src = read_cpu_reg(s, rn, sf); if (!sf) {
tcg_gen_mov_i64(tcg_rd, tcg_src); tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
/* continue: */
gen_set_label(label_continue);
} }
} }