mirror of https://github.com/xemu-project/xemu.git
include/hw/cxl/cxl_device: Rename mem_size as static_mem_size for type3 memory devices
Rename mem_size as static_mem_size for type3 memdev to cover static RAM and pmem capacity, preparing for the introduction of dynamic capacity to support dynamic capacity devices. Reviewed-by: Gregory Price <gregory.price@memverge.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Fan Ni <fan.ni@samsung.com> Message-Id: <20240523174651.1089554-6-nifan.cxl@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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@ -803,7 +803,7 @@ static CXLRetCode cmd_identify_memory_device(const struct cxl_cmd *cmd,
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snprintf(id->fw_revision, 0x10, "BWFW VERSION %02d", 0);
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stq_le_p(&id->total_capacity,
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cxl_dstate->mem_size / CXL_CAPACITY_MULTIPLIER);
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cxl_dstate->static_mem_size / CXL_CAPACITY_MULTIPLIER);
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stq_le_p(&id->persistent_capacity,
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cxl_dstate->pmem_size / CXL_CAPACITY_MULTIPLIER);
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stq_le_p(&id->volatile_capacity,
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@ -1179,7 +1179,7 @@ static CXLRetCode cmd_media_clear_poison(const struct cxl_cmd *cmd,
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struct clear_poison_pl *in = (void *)payload_in;
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dpa = ldq_le_p(&in->dpa);
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if (dpa + CXL_CACHE_LINE_SIZE > cxl_dstate->mem_size) {
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if (dpa + CXL_CACHE_LINE_SIZE > cxl_dstate->static_mem_size) {
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return CXL_MBOX_INVALID_PA;
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}
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@ -608,7 +608,7 @@ static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp)
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}
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address_space_init(&ct3d->hostvmem_as, vmr, v_name);
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ct3d->cxl_dstate.vmem_size = memory_region_size(vmr);
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ct3d->cxl_dstate.mem_size += memory_region_size(vmr);
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ct3d->cxl_dstate.static_mem_size += memory_region_size(vmr);
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g_free(v_name);
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}
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@ -631,7 +631,7 @@ static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp)
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}
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address_space_init(&ct3d->hostpmem_as, pmr, p_name);
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ct3d->cxl_dstate.pmem_size = memory_region_size(pmr);
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ct3d->cxl_dstate.mem_size += memory_region_size(pmr);
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ct3d->cxl_dstate.static_mem_size += memory_region_size(pmr);
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g_free(p_name);
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}
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@ -837,7 +837,7 @@ static int cxl_type3_hpa_to_as_and_dpa(CXLType3Dev *ct3d,
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return -EINVAL;
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}
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if (*dpa_offset > ct3d->cxl_dstate.mem_size) {
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if (*dpa_offset > ct3d->cxl_dstate.static_mem_size) {
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return -EINVAL;
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}
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@ -1010,7 +1010,7 @@ static bool set_cacheline(CXLType3Dev *ct3d, uint64_t dpa_offset, uint8_t *data)
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return false;
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}
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if (dpa_offset + CXL_CACHE_LINE_SIZE > ct3d->cxl_dstate.mem_size) {
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if (dpa_offset + CXL_CACHE_LINE_SIZE > ct3d->cxl_dstate.static_mem_size) {
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return false;
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}
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@ -234,7 +234,7 @@ typedef struct cxl_device_state {
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} timestamp;
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/* memory region size, HDM */
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uint64_t mem_size;
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uint64_t static_mem_size;
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uint64_t pmem_size;
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uint64_t vmem_size;
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