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target/hppa: Implement STDBY 

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-09-20 17:00:23 +02:00
parent a8966ba70a
commit 25460fc5a7
4 changed files with 213 additions and 5 deletions
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5
target/hppa/helper.h
View File

@ -16,6 +16,11 @@ DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tr)
DEF_HELPER_FLAGS_3(stby_e, TCG_CALL_NO_WG, void, env, tl, tr) DEF_HELPER_FLAGS_3(stby_e, TCG_CALL_NO_WG, void, env, tl, tr)
DEF_HELPER_FLAGS_3(stby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tr) DEF_HELPER_FLAGS_3(stby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tr)
DEF_HELPER_FLAGS_3(stdby_b, TCG_CALL_NO_WG, void, env, tl, tr)
DEF_HELPER_FLAGS_3(stdby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tr)
DEF_HELPER_FLAGS_3(stdby_e, TCG_CALL_NO_WG, void, env, tl, tr)
DEF_HELPER_FLAGS_3(stdby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tr)
DEF_HELPER_FLAGS_1(ldc_check, TCG_CALL_NO_RWG, void, tl) DEF_HELPER_FLAGS_1(ldc_check, TCG_CALL_NO_RWG, void, tl)
DEF_HELPER_FLAGS_4(probe, TCG_CALL_NO_WG, tr, env, tl, i32, i32) DEF_HELPER_FLAGS_4(probe, TCG_CALL_NO_WG, tr, env, tl, i32, i32)

1
target/hppa/insns.decode
View File

@ -228,6 +228,7 @@ lda 000011 ..... ..... .. . 0 -- 0100 ...... @ldstx size=3
sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 size=2 sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 size=2
sta 000011 ..... ..... .. . 1 -- 1111 ...... @stim5 size=3 sta 000011 ..... ..... .. . 1 -- 1111 ...... @stim5 size=3
stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=%im5_0 stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=%im5_0
stdby 000011 b:5 r:5 sp:2 a:1 1 -- 1101 m:1 ..... disp=%im5_0
@fldstwx ...... b:5 x:5 sp:2 scale:1 ....... m:1 ..... \ @fldstwx ...... b:5 x:5 sp:2 scale:1 ....... m:1 ..... \
&ldst t=%rt64 disp=0 size=2 &ldst t=%rt64 disp=0 size=2

178
target/hppa/op_helper.c
View File

@ -56,11 +56,11 @@ void HELPER(tcond)(CPUHPPAState *env, target_ureg cond)
} }
} }
static void atomic_store_3(CPUHPPAState *env, target_ulong addr, static void atomic_store_mask32(CPUHPPAState *env, target_ulong addr,
uint32_t val, uintptr_t ra) uint32_t val, uint32_t mask, uintptr_t ra)
{ {
int mmu_idx = cpu_mmu_index(env, 0); int mmu_idx = cpu_mmu_index(env, 0);
uint32_t old, new, cmp, mask, *haddr; uint32_t old, new, cmp, *haddr;
void *vaddr; void *vaddr;
vaddr = probe_access(env, addr, 3, MMU_DATA_STORE, mmu_idx, ra); vaddr = probe_access(env, addr, 3, MMU_DATA_STORE, mmu_idx, ra);
@ -81,6 +81,35 @@ static void atomic_store_3(CPUHPPAState *env, target_ulong addr,
} }
} }
static void atomic_store_mask64(CPUHPPAState *env, target_ulong addr,
uint64_t val, uint64_t mask,
int size, uintptr_t ra)
{
#ifdef CONFIG_ATOMIC64
int mmu_idx = cpu_mmu_index(env, 0);
uint64_t old, new, cmp, *haddr;
void *vaddr;
vaddr = probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, ra);
if (vaddr == NULL) {
cpu_loop_exit_atomic(env_cpu(env), ra);
}
haddr = (uint64_t *)((uintptr_t)vaddr & -8);
old = *haddr;
while (1) {
new = be32_to_cpu((cpu_to_be32(old) & ~mask) | (val & mask));
cmp = qatomic_cmpxchg__nocheck(haddr, old, new);
if (cmp == old) {
return;
}
old = cmp;
}
#else
cpu_loop_exit_atomic(env_cpu(env), ra);
#endif
}
static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ureg val, static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ureg val,
bool parallel, uintptr_t ra) bool parallel, uintptr_t ra)
{ {
@ -94,7 +123,7 @@ static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ureg val,
case 1: case 1:
/* The 3 byte store must appear atomic. */ /* The 3 byte store must appear atomic. */
if (parallel) { if (parallel) {
atomic_store_3(env, addr, val, ra); atomic_store_mask32(env, addr, val, 0x00ffffffu, ra);
} else { } else {
cpu_stb_data_ra(env, addr, val >> 16, ra); cpu_stb_data_ra(env, addr, val >> 16, ra);
cpu_stw_data_ra(env, addr + 1, val, ra); cpu_stw_data_ra(env, addr + 1, val, ra);
@ -106,6 +135,62 @@ static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ureg val,
} }
} }
static void do_stdby_b(CPUHPPAState *env, target_ulong addr, uint64_t val,
bool parallel, uintptr_t ra)
{
switch (addr & 7) {
case 7:
cpu_stb_data_ra(env, addr, val, ra);
break;
case 6:
cpu_stw_data_ra(env, addr, val, ra);
break;
case 5:
/* The 3 byte store must appear atomic. */
if (parallel) {
atomic_store_mask32(env, addr, val, 0x00ffffffu, ra);
} else {
cpu_stb_data_ra(env, addr, val >> 16, ra);
cpu_stw_data_ra(env, addr + 1, val, ra);
}
break;
case 4:
cpu_stl_data_ra(env, addr, val, ra);
break;
case 3:
/* The 5 byte store must appear atomic. */
if (parallel) {
atomic_store_mask64(env, addr, val, 0x000000ffffffffffull, 5, ra);
} else {
cpu_stb_data_ra(env, addr, val >> 32, ra);
cpu_stl_data_ra(env, addr + 1, val, ra);
}
break;
case 2:
/* The 6 byte store must appear atomic. */
if (parallel) {
atomic_store_mask64(env, addr, val, 0x0000ffffffffffffull, 6, ra);
} else {
cpu_stw_data_ra(env, addr, val >> 32, ra);
cpu_stl_data_ra(env, addr + 2, val, ra);
}
break;
case 1:
/* The 7 byte store must appear atomic. */
if (parallel) {
atomic_store_mask64(env, addr, val, 0x00ffffffffffffffull, 7, ra);
} else {
cpu_stb_data_ra(env, addr, val >> 48, ra);
cpu_stw_data_ra(env, addr + 1, val >> 32, ra);
cpu_stl_data_ra(env, addr + 3, val, ra);
}
break;
default:
cpu_stq_data_ra(env, addr, val, ra);
break;
}
}
void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ureg val) void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ureg val)
{ {
do_stby_b(env, addr, val, false, GETPC()); do_stby_b(env, addr, val, false, GETPC());
@ -117,6 +202,17 @@ void HELPER(stby_b_parallel)(CPUHPPAState *env, target_ulong addr,
do_stby_b(env, addr, val, true, GETPC()); do_stby_b(env, addr, val, true, GETPC());
} }
void HELPER(stdby_b)(CPUHPPAState *env, target_ulong addr, target_ureg val)
{
do_stdby_b(env, addr, val, false, GETPC());
}
void HELPER(stdby_b_parallel)(CPUHPPAState *env, target_ulong addr,
target_ureg val)
{
do_stdby_b(env, addr, val, true, GETPC());
}
static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ureg val, static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ureg val,
bool parallel, uintptr_t ra) bool parallel, uintptr_t ra)
{ {
@ -124,7 +220,68 @@ static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ureg val,
case 3: case 3:
/* The 3 byte store must appear atomic. */ /* The 3 byte store must appear atomic. */
if (parallel) { if (parallel) {
atomic_store_3(env, addr - 3, val, ra); atomic_store_mask32(env, addr - 3, val, 0xffffff00u, ra);
} else {
cpu_stw_data_ra(env, addr - 3, val >> 16, ra);
cpu_stb_data_ra(env, addr - 1, val >> 8, ra);
}
break;
case 2:
cpu_stw_data_ra(env, addr - 2, val >> 16, ra);
break;
case 1:
cpu_stb_data_ra(env, addr - 1, val >> 24, ra);
break;
default:
/* Nothing is stored, but protection is checked and the
cacheline is marked dirty. */
probe_write(env, addr, 0, cpu_mmu_index(env, 0), ra);
break;
}
}
static void do_stdby_e(CPUHPPAState *env, target_ulong addr, uint64_t val,
bool parallel, uintptr_t ra)
{
switch (addr & 7) {
case 7:
/* The 7 byte store must appear atomic. */
if (parallel) {
atomic_store_mask64(env, addr - 7, val,
0xffffffffffffff00ull, 7, ra);
} else {
cpu_stl_data_ra(env, addr - 7, val >> 32, ra);
cpu_stw_data_ra(env, addr - 3, val >> 16, ra);
cpu_stb_data_ra(env, addr - 1, val >> 8, ra);
}
break;
case 6:
/* The 6 byte store must appear atomic. */
if (parallel) {
atomic_store_mask64(env, addr - 6, val,
0xffffffffffff0000ull, 6, ra);
} else {
cpu_stl_data_ra(env, addr - 6, val >> 32, ra);
cpu_stw_data_ra(env, addr - 2, val >> 16, ra);
}
break;
case 5:
/* The 5 byte store must appear atomic. */
if (parallel) {
atomic_store_mask64(env, addr - 5, val,
0xffffffffff000000ull, 5, ra);
} else {
cpu_stl_data_ra(env, addr - 5, val >> 32, ra);
cpu_stb_data_ra(env, addr - 1, val >> 24, ra);
}
break;
case 4:
cpu_stl_data_ra(env, addr - 4, val >> 32, ra);
break;
case 3:
/* The 3 byte store must appear atomic. */
if (parallel) {
atomic_store_mask32(env, addr - 3, val, 0xffffff00u, ra);
} else { } else {
cpu_stw_data_ra(env, addr - 3, val >> 16, ra); cpu_stw_data_ra(env, addr - 3, val >> 16, ra);
cpu_stb_data_ra(env, addr - 1, val >> 8, ra); cpu_stb_data_ra(env, addr - 1, val >> 8, ra);
@ -155,6 +312,17 @@ void HELPER(stby_e_parallel)(CPUHPPAState *env, target_ulong addr,
do_stby_e(env, addr, val, true, GETPC()); do_stby_e(env, addr, val, true, GETPC());
} }
void HELPER(stdby_e)(CPUHPPAState *env, target_ulong addr, target_ureg val)
{
do_stdby_e(env, addr, val, false, GETPC());
}
void HELPER(stdby_e_parallel)(CPUHPPAState *env, target_ulong addr,
target_ureg val)
{
do_stdby_e(env, addr, val, true, GETPC());
}
void HELPER(ldc_check)(target_ulong addr) void HELPER(ldc_check)(target_ulong addr)
{ {
if (unlikely(addr & 0xf)) { if (unlikely(addr & 0xf)) {

34
target/hppa/translate.c
View File

@ -3052,6 +3052,40 @@ static bool trans_stby(DisasContext *ctx, arg_stby *a)
return nullify_end(ctx); return nullify_end(ctx);
} }
static bool trans_stdby(DisasContext *ctx, arg_stby *a)
{
TCGv_reg ofs, val;
TCGv_tl addr;
if (!ctx->is_pa20) {
return false;
}
nullify_over(ctx);
form_gva(ctx, &addr, &ofs, a->b, 0, 0, a->disp, a->sp, a->m,
ctx->mmu_idx == MMU_PHYS_IDX);
val = load_gpr(ctx, a->r);
if (a->a) {
if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
gen_helper_stdby_e_parallel(tcg_env, addr, val);
} else {
gen_helper_stdby_e(tcg_env, addr, val);
}
} else {
if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
gen_helper_stdby_b_parallel(tcg_env, addr, val);
} else {
gen_helper_stdby_b(tcg_env, addr, val);
}
}
if (a->m) {
tcg_gen_andi_reg(ofs, ofs, ~7);
save_gpr(ctx, a->b, ofs);
}
return nullify_end(ctx);
}
static bool trans_lda(DisasContext *ctx, arg_ldst *a) static bool trans_lda(DisasContext *ctx, arg_ldst *a)
{ {
int hold_mmu_idx = ctx->mmu_idx; int hold_mmu_idx = ctx->mmu_idx;