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target/arm: Improve masking of SCR RES0 bits 

Protect reads of aa64 id registers with ARM_CP_STATE_AA64.
Use this as a simpler test than arm_el_is_aa64, since EL3
cannot change mode.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2020-06-25 20:31:00 -07:00 committed by Peter Maydell
parent c7fd0baac0
commit 252e8c6966
1 changed files with 8 additions and 7 deletions
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15
target/arm/helper.c
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@ -2011,9 +2011,16 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
uint32_t valid_mask = 0x3fff; uint32_t valid_mask = 0x3fff;
ARMCPU *cpu = env_archcpu(env); ARMCPU *cpu = env_archcpu(env);
if (arm_el_is_aa64(env, 3)) { if (ri->state == ARM_CP_STATE_AA64) {
value |= SCR_FW | SCR_AW; /* these two bits are RES1. */ value |= SCR_FW | SCR_AW; /* these two bits are RES1. */
valid_mask &= ~SCR_NET; valid_mask &= ~SCR_NET;
if (cpu_isar_feature(aa64_lor, cpu)) {
valid_mask |= SCR_TLOR;
}
if (cpu_isar_feature(aa64_pauth, cpu)) {
valid_mask |= SCR_API | SCR_APK;
}
} else { } else {
valid_mask &= ~(SCR_RW | SCR_ST); valid_mask &= ~(SCR_RW | SCR_ST);
} }
@ -2032,12 +2039,6 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
valid_mask &= ~SCR_SMD; valid_mask &= ~SCR_SMD;
} }
} }
if (cpu_isar_feature(aa64_lor, cpu)) {
valid_mask |= SCR_TLOR;
}
if (cpu_isar_feature(aa64_pauth, cpu)) {
valid_mask |= SCR_API | SCR_APK;
}
/* Clear all-context RES0 bits. */ /* Clear all-context RES0 bits. */
value &= valid_mask; value &= valid_mask;