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target/m68k: Fix MACSR to CCR 

First, we were writing to the entire SR register, instead
of only the flags portion.  Second, we were not clearing C
as per the documentation (X was cleared via the 0xf mask).

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20220913142818.7802-2-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
This commit is contained in:
Richard Henderson 2022-09-13 15:28:17 +01:00 committed by Laurent Vivier
parent 5934dae7a7
commit 24ec52f91d
1 changed files with 4 additions and 2 deletions
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6
target/m68k/translate.c
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@ -5912,8 +5912,10 @@ DISAS_INSN(from_mext)
DISAS_INSN(macsr_to_ccr)
{
TCGv tmp = tcg_temp_new();
tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf);
gen_helper_set_sr(cpu_env, tmp);
/* Note that X and C are always cleared. */
tcg_gen_andi_i32(tmp, QREG_MACSR, CCF_N | CCF_Z | CCF_V);
gen_helper_set_ccr(cpu_env, tmp);
tcg_temp_free(tmp);
set_cc_op(s, CC_OP_FLAGS);
}