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target/arm: Move sve check into gen_gvec_fn_ppp
Combined with the check already present in gen_mov_p, we can simplify some special cases in trans_AND_pppp and trans_BIC_pppp. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220527181907.189259-80-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -370,13 +370,16 @@ static void do_dupi_z(DisasContext *s, int rd, uint64_t word)
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}
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/* Invoke a vector expander on three Pregs. */
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static void gen_gvec_fn_ppp(DisasContext *s, GVecGen3Fn *gvec_fn,
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static bool gen_gvec_fn_ppp(DisasContext *s, GVecGen3Fn *gvec_fn,
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int rd, int rn, int rm)
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{
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unsigned psz = pred_gvec_reg_size(s);
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gvec_fn(MO_64, pred_full_reg_offset(s, rd),
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pred_full_reg_offset(s, rn),
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pred_full_reg_offset(s, rm), psz, psz);
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if (sve_access_check(s)) {
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unsigned psz = pred_gvec_reg_size(s);
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gvec_fn(MO_64, pred_full_reg_offset(s, rd),
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pred_full_reg_offset(s, rn),
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pred_full_reg_offset(s, rm), psz, psz);
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}
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return true;
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}
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/* Invoke a vector move on two Pregs. */
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@ -1317,19 +1320,13 @@ static bool trans_AND_pppp(DisasContext *s, arg_rprr_s *a)
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};
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if (!a->s) {
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if (!sve_access_check(s)) {
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return true;
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}
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if (a->rn == a->rm) {
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if (a->pg == a->rn) {
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do_mov_p(s, a->rd, a->rn);
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} else {
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gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->pg);
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return do_mov_p(s, a->rd, a->rn);
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}
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return true;
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return gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->pg);
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} else if (a->pg == a->rn || a->pg == a->rm) {
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gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->rm);
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return true;
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return gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->rm);
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}
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}
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return do_pppp_flags(s, a, &op);
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@ -1358,10 +1355,7 @@ static bool trans_BIC_pppp(DisasContext *s, arg_rprr_s *a)
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};
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if (!a->s && a->pg == a->rn) {
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if (sve_access_check(s)) {
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gen_gvec_fn_ppp(s, tcg_gen_gvec_andc, a->rd, a->rn, a->rm);
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}
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return true;
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return gen_gvec_fn_ppp(s, tcg_gen_gvec_andc, a->rd, a->rn, a->rm);
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}
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return do_pppp_flags(s, a, &op);
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}
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