From 23ab6d8813685c38fd1d87f573dded9fe37ee17f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Wed, 12 Jan 2022 11:28:26 +0100 Subject: [PATCH] target/ppc: Add popcntb instruction to POWER5+ processors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit popcntb instruction was added in ISA v2.02. Add support for POWER5+ processors since they implement ISA v2.03. PPC970 CPUs implement v2.01 and do not support popcntb. Signed-off-by: Cédric Le Goater Reviewed-by: Fabiano Rosas Message-Id: <20220105095142.3990430-2-clg@kaod.org> Signed-off-by: Cédric Le Goater --- target/ppc/cpu_init.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index cc93bff3fa..f15a52259c 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6957,6 +6957,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_64B | + PPC_POPCNTB | PPC_SEGMENT_64B | PPC_SLBI; pcc->insns_flags2 = PPC2_FP_CVT_S64; pcc->msr_mask = (1ull << MSR_SF) |