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hw/mem/cxl-type3: Add MSIX support 

This will be used by several upcoming patch sets so break it out
such that it doesn't matter which one lands first.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20221014151045.24781-3-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Jonathan Cameron 2022-10-14 16:10:42 +01:00 committed by Michael S. Tsirkin
parent 5fb52f6cc8
commit 23325c8df4
1 changed files with 9 additions and 0 deletions
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9
hw/mem/cxl_type3.c
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@ -13,6 +13,7 @@
#include "qemu/rcu.h" #include "qemu/rcu.h"
#include "sysemu/hostmem.h" #include "sysemu/hostmem.h"
#include "hw/cxl/cxl.h" #include "hw/cxl/cxl.h"
#include "hw/pci/msix.h"
/* /*
* Null value of all Fs suggested by IEEE RA guidelines for use of * Null value of all Fs suggested by IEEE RA guidelines for use of
@ -146,6 +147,8 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
ComponentRegisters *regs = &cxl_cstate->crb; ComponentRegisters *regs = &cxl_cstate->crb;
MemoryRegion *mr = &regs->component_registers; MemoryRegion *mr = &regs->component_registers;
uint8_t *pci_conf = pci_dev->config; uint8_t *pci_conf = pci_dev->config;
unsigned short msix_num = 1;
int i;
if (!cxl_setup_memory(ct3d, errp)) { if (!cxl_setup_memory(ct3d, errp)) {
return; return;
@ -180,6 +183,12 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_SPACE_MEMORY |
PCI_BASE_ADDRESS_MEM_TYPE_64, PCI_BASE_ADDRESS_MEM_TYPE_64,
&ct3d->cxl_dstate.device_registers); &ct3d->cxl_dstate.device_registers);
/* MSI(-X) Initailization */
msix_init_exclusive_bar(pci_dev, msix_num, 4, NULL);
for (i = 0; i < msix_num; i++) {
msix_vector_use(pci_dev, i);
}
} }
static void ct3_exit(PCIDevice *pci_dev) static void ct3_exit(PCIDevice *pci_dev)