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target/riscv: Set opcode to env->bins for illegal/virtual instruction fault 

decode_save_opc() will not work for generate_exception(), since 0 is passed
to riscv_raise_exception() as pc in helper_raise_exception(), and bins will
not be restored in this case.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230330034636.44585-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li 2023-03-30 11:46:36 +08:00 committed by Alistair Francis
parent 77dff6509c
commit 22c2f87ab2
1 changed files with 2 additions and 0 deletions
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2
target/riscv/insn_trans/trans_rvh.c.inc
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@ -20,6 +20,8 @@
static bool check_access(DisasContext *ctx)
{
if (!ctx->hlsx) {
tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
offsetof(CPURISCVState, bins));
if (ctx->virt_enabled) {
generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
} else {