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target/tricore: Swap src and dst reg for RCRR_INSERT 

Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-10-kbastian@mail.uni-paderborn.de>
This commit is contained in:
Bastian Koppelmann 2023-08-28 13:26:49 +02:00
parent 23fa6f56b3
commit 222ff2d358
3 changed files with 18 additions and 4 deletions
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8
target/tricore/translate.c
View File

@ -8223,12 +8223,12 @@ static void decode_32Bit_opc(DisasContext *ctx)
temp2 = tcg_temp_new(); /* width*/
temp3 = tcg_temp_new(); /* pos */
CHECK_REG_PAIR(r3);
CHECK_REG_PAIR(r2);
tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f);
tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
tcg_gen_andi_tl(temp2, cpu_gpr_d[r2 + 1], 0x1f);
tcg_gen_andi_tl(temp3, cpu_gpr_d[r2], 0x1f);
gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3);
gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, temp2, temp3);
break;
/* RCRW Format */
case OPCM_32_RCRW_MASK_INSERT:

9
tests/tcg/tricore/asm/macros.h
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@ -169,6 +169,15 @@ test_ ## num: \
insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm1, imm2; \
)
#define TEST_D_DIE(insn, num, result, rs1, imm1, rs2_lo, rs2_hi)\
TEST_CASE(num, DREG_CALC_RESULT, result, \
LI(DREG_RS1, rs1); \
LI(EREG_RS2_LO, rs2_lo); \
LI(EREG_RS2_HI, rs2_hi); \
rstv; \
insn DREG_CALC_RESULT, DREG_RS1, imm1, EREG_RS2; \
)
#define TEST_D_DIII(insn, num, result, rs1, imm1, imm2, imm3)\
TEST_CASE(num, DREG_CALC_RESULT, result, \
LI(DREG_RS1, rs1); \

5
tests/tcg/tricore/asm/test_insert.S
View File

@ -15,4 +15,9 @@ _start:
# | | | | | | |
TEST_D_DDII(insert, 4, 0x03c1e53c, 0x03c1e53c, 0x45821385, 0x7 ,0x0)
# insn num result rs1 imm1 rs2_h rs2_l
# | | | | | | |
TEST_D_DIE(insert, 5, 0xe30c308d, 0xe30c308d ,0x3 , 0x00000000 ,0x00000000)
TEST_D_DIE(insert, 6, 0x669b0120, 0x669b2820 ,0x2 , 0x5530a1c7 ,0x3a2b0f67)
TEST_PASSFAIL