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target-arm/translate-a64.c: Remove dead ?: in disas_simd_3same_int() 

In disas_simd_3same_int(), none of the instructions permit is_q
to be false with size == 3 (this would be a vector operation with
a one-element vector, and the instruction set encodes those as
scalar operations). Replace the always-true ?: check with an
assert.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1402171881-14343-3-git-send-email-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2014-06-19 18:06:24 +01:00
parent 5661ae6be2
commit 220ad4ca84
1 changed files with 2 additions and 1 deletions
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3
target-arm/translate-a64.c
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@ -9052,7 +9052,8 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
}
if (size == 3) {
for (pass = 0; pass < (is_q ? 2 : 1); pass++) {
assert(is_q);
for (pass = 0; pass < 2; pass++) {
TCGv_i64 tcg_op1 = tcg_temp_new_i64();
TCGv_i64 tcg_op2 = tcg_temp_new_i64();
TCGv_i64 tcg_res = tcg_temp_new_i64();