mirror of https://github.com/xemu-project/xemu.git
update linux headers to kvm/next
This updates the kvm headers to commit d3714010c307d26df251c45be9cd12ab6d41f0c4 KVM: x86: emulator_cmpxchg_emulated should mark_page_dirty in kvm/next. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
This commit is contained in:
parent
d5001cf787
commit
216db403d0
|
@ -119,6 +119,26 @@ struct kvm_arch_memory_slot {
|
||||||
#define KVM_REG_ARM_32_CRN_MASK 0x0000000000007800
|
#define KVM_REG_ARM_32_CRN_MASK 0x0000000000007800
|
||||||
#define KVM_REG_ARM_32_CRN_SHIFT 11
|
#define KVM_REG_ARM_32_CRN_SHIFT 11
|
||||||
|
|
||||||
|
#define ARM_CP15_REG_SHIFT_MASK(x,n) \
|
||||||
|
(((x) << KVM_REG_ARM_ ## n ## _SHIFT) & KVM_REG_ARM_ ## n ## _MASK)
|
||||||
|
|
||||||
|
#define __ARM_CP15_REG(op1,crn,crm,op2) \
|
||||||
|
(KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT) | \
|
||||||
|
ARM_CP15_REG_SHIFT_MASK(op1, OPC1) | \
|
||||||
|
ARM_CP15_REG_SHIFT_MASK(crn, 32_CRN) | \
|
||||||
|
ARM_CP15_REG_SHIFT_MASK(crm, CRM) | \
|
||||||
|
ARM_CP15_REG_SHIFT_MASK(op2, 32_OPC2))
|
||||||
|
|
||||||
|
#define ARM_CP15_REG32(...) (__ARM_CP15_REG(__VA_ARGS__) | KVM_REG_SIZE_U32)
|
||||||
|
|
||||||
|
#define __ARM_CP15_REG64(op1,crm) \
|
||||||
|
(__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64)
|
||||||
|
#define ARM_CP15_REG64(...) __ARM_CP15_REG64(__VA_ARGS__)
|
||||||
|
|
||||||
|
#define KVM_REG_ARM_TIMER_CTL ARM_CP15_REG32(0, 14, 3, 1)
|
||||||
|
#define KVM_REG_ARM_TIMER_CNT ARM_CP15_REG64(1, 14)
|
||||||
|
#define KVM_REG_ARM_TIMER_CVAL ARM_CP15_REG64(3, 14)
|
||||||
|
|
||||||
/* Normal registers are mapped as coprocessor 16. */
|
/* Normal registers are mapped as coprocessor 16. */
|
||||||
#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
|
#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
|
||||||
#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / 4)
|
#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / 4)
|
||||||
|
@ -143,6 +163,14 @@ struct kvm_arch_memory_slot {
|
||||||
#define KVM_REG_ARM_VFP_FPINST 0x1009
|
#define KVM_REG_ARM_VFP_FPINST 0x1009
|
||||||
#define KVM_REG_ARM_VFP_FPINST2 0x100A
|
#define KVM_REG_ARM_VFP_FPINST2 0x100A
|
||||||
|
|
||||||
|
/* Device Control API: ARM VGIC */
|
||||||
|
#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
|
||||||
|
#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
|
||||||
|
#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
|
||||||
|
#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
|
||||||
|
#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
|
||||||
|
#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
|
||||||
|
#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
|
||||||
|
|
||||||
/* KVM_IRQ_LINE irq field index values */
|
/* KVM_IRQ_LINE irq field index values */
|
||||||
#define KVM_ARM_IRQ_TYPE_SHIFT 24
|
#define KVM_ARM_IRQ_TYPE_SHIFT 24
|
||||||
|
|
|
@ -55,8 +55,9 @@ struct kvm_regs {
|
||||||
#define KVM_ARM_TARGET_AEM_V8 0
|
#define KVM_ARM_TARGET_AEM_V8 0
|
||||||
#define KVM_ARM_TARGET_FOUNDATION_V8 1
|
#define KVM_ARM_TARGET_FOUNDATION_V8 1
|
||||||
#define KVM_ARM_TARGET_CORTEX_A57 2
|
#define KVM_ARM_TARGET_CORTEX_A57 2
|
||||||
|
#define KVM_ARM_TARGET_XGENE_POTENZA 3
|
||||||
|
|
||||||
#define KVM_ARM_NUM_TARGETS 3
|
#define KVM_ARM_NUM_TARGETS 4
|
||||||
|
|
||||||
/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
|
/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
|
||||||
#define KVM_ARM_DEVICE_TYPE_SHIFT 0
|
#define KVM_ARM_DEVICE_TYPE_SHIFT 0
|
||||||
|
@ -129,6 +130,33 @@ struct kvm_arch_memory_slot {
|
||||||
#define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007
|
#define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007
|
||||||
#define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0
|
#define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0
|
||||||
|
|
||||||
|
#define ARM64_SYS_REG_SHIFT_MASK(x,n) \
|
||||||
|
(((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \
|
||||||
|
KVM_REG_ARM64_SYSREG_ ## n ## _MASK)
|
||||||
|
|
||||||
|
#define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \
|
||||||
|
(KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \
|
||||||
|
ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \
|
||||||
|
ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
|
||||||
|
ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
|
||||||
|
ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
|
||||||
|
ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
|
||||||
|
|
||||||
|
#define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64)
|
||||||
|
|
||||||
|
#define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1)
|
||||||
|
#define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2)
|
||||||
|
#define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2)
|
||||||
|
|
||||||
|
/* Device Control API: ARM VGIC */
|
||||||
|
#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
|
||||||
|
#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
|
||||||
|
#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
|
||||||
|
#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
|
||||||
|
#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
|
||||||
|
#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
|
||||||
|
#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
|
||||||
|
|
||||||
/* KVM_IRQ_LINE irq field index values */
|
/* KVM_IRQ_LINE irq field index values */
|
||||||
#define KVM_ARM_IRQ_TYPE_SHIFT 24
|
#define KVM_ARM_IRQ_TYPE_SHIFT 24
|
||||||
#define KVM_ARM_IRQ_TYPE_MASK 0xff
|
#define KVM_ARM_IRQ_TYPE_MASK 0xff
|
||||||
|
|
|
@ -545,6 +545,7 @@ struct kvm_get_htab_header {
|
||||||
#define KVM_REG_PPC_TCSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb1)
|
#define KVM_REG_PPC_TCSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb1)
|
||||||
#define KVM_REG_PPC_PID (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb2)
|
#define KVM_REG_PPC_PID (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb2)
|
||||||
#define KVM_REG_PPC_ACOP (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb3)
|
#define KVM_REG_PPC_ACOP (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb3)
|
||||||
|
#define KVM_REG_PPC_WORT (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb4)
|
||||||
|
|
||||||
#define KVM_REG_PPC_VRSAVE (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb4)
|
#define KVM_REG_PPC_VRSAVE (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb4)
|
||||||
#define KVM_REG_PPC_LPCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb5)
|
#define KVM_REG_PPC_LPCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb5)
|
||||||
|
@ -553,6 +554,8 @@ struct kvm_get_htab_header {
|
||||||
/* Architecture compatibility level */
|
/* Architecture compatibility level */
|
||||||
#define KVM_REG_PPC_ARCH_COMPAT (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb7)
|
#define KVM_REG_PPC_ARCH_COMPAT (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb7)
|
||||||
|
|
||||||
|
#define KVM_REG_PPC_DABRX (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb8)
|
||||||
|
|
||||||
/* Transactional Memory checkpointed state:
|
/* Transactional Memory checkpointed state:
|
||||||
* This is all GPRs, all VSX regs and a subset of SPRs
|
* This is all GPRs, all VSX regs and a subset of SPRs
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -16,6 +16,22 @@
|
||||||
|
|
||||||
#define __KVM_S390
|
#define __KVM_S390
|
||||||
|
|
||||||
|
/* Device control API: s390-specific devices */
|
||||||
|
#define KVM_DEV_FLIC_GET_ALL_IRQS 1
|
||||||
|
#define KVM_DEV_FLIC_ENQUEUE 2
|
||||||
|
#define KVM_DEV_FLIC_CLEAR_IRQS 3
|
||||||
|
#define KVM_DEV_FLIC_APF_ENABLE 4
|
||||||
|
#define KVM_DEV_FLIC_APF_DISABLE_WAIT 5
|
||||||
|
/*
|
||||||
|
* We can have up to 4*64k pending subchannels + 8 adapter interrupts,
|
||||||
|
* as well as up to ASYNC_PF_PER_VCPU*KVM_MAX_VCPUS pfault done interrupts.
|
||||||
|
* There are also sclp and machine checks. This gives us
|
||||||
|
* sizeof(kvm_s390_irq)*(4*65536+8+64*64+1+1) = 72 * 266250 = 19170000
|
||||||
|
* Lets round up to 8192 pages.
|
||||||
|
*/
|
||||||
|
#define KVM_S390_MAX_FLOAT_IRQS 266250
|
||||||
|
#define KVM_S390_FLIC_MAX_BUFFER 0x2000000
|
||||||
|
|
||||||
/* for KVM_GET_REGS and KVM_SET_REGS */
|
/* for KVM_GET_REGS and KVM_SET_REGS */
|
||||||
struct kvm_regs {
|
struct kvm_regs {
|
||||||
/* general purpose regs for s390 */
|
/* general purpose regs for s390 */
|
||||||
|
@ -57,4 +73,7 @@ struct kvm_sync_regs {
|
||||||
#define KVM_REG_S390_EPOCHDIFF (KVM_REG_S390 | KVM_REG_SIZE_U64 | 0x2)
|
#define KVM_REG_S390_EPOCHDIFF (KVM_REG_S390 | KVM_REG_SIZE_U64 | 0x2)
|
||||||
#define KVM_REG_S390_CPU_TIMER (KVM_REG_S390 | KVM_REG_SIZE_U64 | 0x3)
|
#define KVM_REG_S390_CPU_TIMER (KVM_REG_S390 | KVM_REG_SIZE_U64 | 0x3)
|
||||||
#define KVM_REG_S390_CLOCK_COMP (KVM_REG_S390 | KVM_REG_SIZE_U64 | 0x4)
|
#define KVM_REG_S390_CLOCK_COMP (KVM_REG_S390 | KVM_REG_SIZE_U64 | 0x4)
|
||||||
|
#define KVM_REG_S390_PFTOKEN (KVM_REG_S390 | KVM_REG_SIZE_U64 | 0x5)
|
||||||
|
#define KVM_REG_S390_PFCOMPARE (KVM_REG_S390 | KVM_REG_SIZE_U64 | 0x6)
|
||||||
|
#define KVM_REG_S390_PFSELECT (KVM_REG_S390 | KVM_REG_SIZE_U64 | 0x7)
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -28,6 +28,9 @@
|
||||||
/* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/
|
/* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/
|
||||||
#define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE (1 << 1)
|
#define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE (1 << 1)
|
||||||
|
|
||||||
|
/* A partition's reference time stamp counter (TSC) page */
|
||||||
|
#define HV_X64_MSR_REFERENCE_TSC 0x40000021
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* There is a single feature flag that signifies the presence of the MSR
|
* There is a single feature flag that signifies the presence of the MSR
|
||||||
* that can be used to retrieve both the local APIC Timer frequency as
|
* that can be used to retrieve both the local APIC Timer frequency as
|
||||||
|
@ -149,9 +152,6 @@
|
||||||
/* MSR used to read the per-partition time reference counter */
|
/* MSR used to read the per-partition time reference counter */
|
||||||
#define HV_X64_MSR_TIME_REF_COUNT 0x40000020
|
#define HV_X64_MSR_TIME_REF_COUNT 0x40000020
|
||||||
|
|
||||||
/* A partition's reference time stamp counter (TSC) page */
|
|
||||||
#define HV_X64_MSR_REFERENCE_TSC 0x40000021
|
|
||||||
|
|
||||||
/* MSR used to retrieve the TSC frequency */
|
/* MSR used to retrieve the TSC frequency */
|
||||||
#define HV_X64_MSR_TSC_FREQUENCY 0x40000022
|
#define HV_X64_MSR_TSC_FREQUENCY 0x40000022
|
||||||
|
|
||||||
|
@ -201,6 +201,9 @@
|
||||||
#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK \
|
#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK \
|
||||||
(~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
|
(~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
|
||||||
|
|
||||||
|
#define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001
|
||||||
|
#define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12
|
||||||
|
|
||||||
#define HV_PROCESSOR_POWER_STATE_C0 0
|
#define HV_PROCESSOR_POWER_STATE_C0 0
|
||||||
#define HV_PROCESSOR_POWER_STATE_C1 1
|
#define HV_PROCESSOR_POWER_STATE_C1 1
|
||||||
#define HV_PROCESSOR_POWER_STATE_C2 2
|
#define HV_PROCESSOR_POWER_STATE_C2 2
|
||||||
|
@ -213,4 +216,11 @@
|
||||||
#define HV_STATUS_INVALID_ALIGNMENT 4
|
#define HV_STATUS_INVALID_ALIGNMENT 4
|
||||||
#define HV_STATUS_INSUFFICIENT_BUFFERS 19
|
#define HV_STATUS_INSUFFICIENT_BUFFERS 19
|
||||||
|
|
||||||
|
typedef struct _HV_REFERENCE_TSC_PAGE {
|
||||||
|
__u32 tsc_sequence;
|
||||||
|
__u32 res1;
|
||||||
|
__u64 tsc_scale;
|
||||||
|
__s64 tsc_offset;
|
||||||
|
} HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE;
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -413,6 +413,8 @@ struct kvm_s390_psw {
|
||||||
#define KVM_S390_PROGRAM_INT 0xfffe0001u
|
#define KVM_S390_PROGRAM_INT 0xfffe0001u
|
||||||
#define KVM_S390_SIGP_SET_PREFIX 0xfffe0002u
|
#define KVM_S390_SIGP_SET_PREFIX 0xfffe0002u
|
||||||
#define KVM_S390_RESTART 0xfffe0003u
|
#define KVM_S390_RESTART 0xfffe0003u
|
||||||
|
#define KVM_S390_INT_PFAULT_INIT 0xfffe0004u
|
||||||
|
#define KVM_S390_INT_PFAULT_DONE 0xfffe0005u
|
||||||
#define KVM_S390_MCHK 0xfffe1000u
|
#define KVM_S390_MCHK 0xfffe1000u
|
||||||
#define KVM_S390_INT_VIRTIO 0xffff2603u
|
#define KVM_S390_INT_VIRTIO 0xffff2603u
|
||||||
#define KVM_S390_INT_SERVICE 0xffff2401u
|
#define KVM_S390_INT_SERVICE 0xffff2401u
|
||||||
|
@ -434,6 +436,69 @@ struct kvm_s390_interrupt {
|
||||||
__u64 parm64;
|
__u64 parm64;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
struct kvm_s390_io_info {
|
||||||
|
__u16 subchannel_id;
|
||||||
|
__u16 subchannel_nr;
|
||||||
|
__u32 io_int_parm;
|
||||||
|
__u32 io_int_word;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct kvm_s390_ext_info {
|
||||||
|
__u32 ext_params;
|
||||||
|
__u32 pad;
|
||||||
|
__u64 ext_params2;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct kvm_s390_pgm_info {
|
||||||
|
__u64 trans_exc_code;
|
||||||
|
__u64 mon_code;
|
||||||
|
__u64 per_address;
|
||||||
|
__u32 data_exc_code;
|
||||||
|
__u16 code;
|
||||||
|
__u16 mon_class_nr;
|
||||||
|
__u8 per_code;
|
||||||
|
__u8 per_atmid;
|
||||||
|
__u8 exc_access_id;
|
||||||
|
__u8 per_access_id;
|
||||||
|
__u8 op_access_id;
|
||||||
|
__u8 pad[3];
|
||||||
|
};
|
||||||
|
|
||||||
|
struct kvm_s390_prefix_info {
|
||||||
|
__u32 address;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct kvm_s390_extcall_info {
|
||||||
|
__u16 code;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct kvm_s390_emerg_info {
|
||||||
|
__u16 code;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct kvm_s390_mchk_info {
|
||||||
|
__u64 cr14;
|
||||||
|
__u64 mcic;
|
||||||
|
__u64 failing_storage_address;
|
||||||
|
__u32 ext_damage_code;
|
||||||
|
__u32 pad;
|
||||||
|
__u8 fixed_logout[16];
|
||||||
|
};
|
||||||
|
|
||||||
|
struct kvm_s390_irq {
|
||||||
|
__u64 type;
|
||||||
|
union {
|
||||||
|
struct kvm_s390_io_info io;
|
||||||
|
struct kvm_s390_ext_info ext;
|
||||||
|
struct kvm_s390_pgm_info pgm;
|
||||||
|
struct kvm_s390_emerg_info emerg;
|
||||||
|
struct kvm_s390_extcall_info extcall;
|
||||||
|
struct kvm_s390_prefix_info prefix;
|
||||||
|
struct kvm_s390_mchk_info mchk;
|
||||||
|
char reserved[64];
|
||||||
|
} u;
|
||||||
|
};
|
||||||
|
|
||||||
/* for KVM_SET_GUEST_DEBUG */
|
/* for KVM_SET_GUEST_DEBUG */
|
||||||
|
|
||||||
#define KVM_GUESTDBG_ENABLE 0x00000001
|
#define KVM_GUESTDBG_ENABLE 0x00000001
|
||||||
|
@ -854,6 +919,8 @@ struct kvm_device_attr {
|
||||||
#define KVM_DEV_VFIO_GROUP 1
|
#define KVM_DEV_VFIO_GROUP 1
|
||||||
#define KVM_DEV_VFIO_GROUP_ADD 1
|
#define KVM_DEV_VFIO_GROUP_ADD 1
|
||||||
#define KVM_DEV_VFIO_GROUP_DEL 2
|
#define KVM_DEV_VFIO_GROUP_DEL 2
|
||||||
|
#define KVM_DEV_TYPE_ARM_VGIC_V2 5
|
||||||
|
#define KVM_DEV_TYPE_FLIC 6
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* ioctls for VM fds
|
* ioctls for VM fds
|
||||||
|
|
Loading…
Reference in New Issue