mirror of https://github.com/xemu-project/xemu.git
e1000: Cosmetic and alignment fixes
This fixes some alignment and cosmetic issues. The changes are made in order that the following patches in this series will look like integral parts of the code surrounding them, while conforming to the coding style. Although some changes in unrelated areas are also made. Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com> Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
This commit is contained in:
Leonid Bloch
Jason Wang
parent
ecc804cac3
commit
20f3e86362
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@ -118,7 +118,7 @@ typedef struct E1000State_st {
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} tx;
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struct {
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uint32_t val_in; // shifted in from guest driver
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uint32_t val_in; /* shifted in from guest driver */
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uint16_t bitnum_in;
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uint16_t bitnum_out;
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uint16_t reading;
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@ -166,7 +166,7 @@ enum {
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defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT),
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defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL),
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defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
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defreg(RA), defreg(MTA), defreg(CRCERRS),defreg(VFTA),
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defreg(RA), defreg(MTA), defreg(CRCERRS), defreg(VFTA),
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defreg(VET), defreg(RDTR), defreg(RADV), defreg(TADV),
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defreg(ITR),
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};
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@ -510,17 +510,19 @@ set_eecd(E1000State *s, int index, uint32_t val)
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s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |
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E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ);
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if (!(E1000_EECD_CS & val)) // CS inactive; nothing to do
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if (!(E1000_EECD_CS & val)) { /* CS inactive; nothing to do */
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return;
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if (E1000_EECD_CS & (val ^ oldval)) { // CS rise edge; reset state
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}
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if (E1000_EECD_CS & (val ^ oldval)) { /* CS rise edge; reset state */
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s->eecd_state.val_in = 0;
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s->eecd_state.bitnum_in = 0;
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s->eecd_state.bitnum_out = 0;
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s->eecd_state.reading = 0;
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}
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if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge
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if (!(E1000_EECD_SK & (val ^ oldval))) { /* no clock edge */
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return;
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if (!(E1000_EECD_SK & val)) { // falling edge
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}
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if (!(E1000_EECD_SK & val)) { /* falling edge */
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s->eecd_state.bitnum_out++;
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return;
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}
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@ -621,12 +623,13 @@ xmit_seg(E1000State *s)
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css = tp->ipcss;
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DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
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frames, tp->size, css);
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if (tp->ip) { // IPv4
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if (tp->ip) { /* IPv4 */
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stw_be_p(tp->data+css+2, tp->size - css);
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stw_be_p(tp->data+css+4,
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be16_to_cpup((uint16_t *)(tp->data+css+4))+frames);
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} else // IPv6
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} else { /* IPv6 */
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stw_be_p(tp->data+css+4, tp->size - css);
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}
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css = tp->tucss;
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len = tp->size - css;
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DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len);
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@ -634,8 +637,8 @@ xmit_seg(E1000State *s)
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sofar = frames * tp->mss;
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stl_be_p(tp->data+css+4, ldl_be_p(tp->data+css+4)+sofar); /* seq */
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if (tp->paylen - sofar > tp->mss)
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tp->data[css + 13] &= ~9; // PSH, FIN
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} else // UDP
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tp->data[css + 13] &= ~9; /* PSH, FIN */
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} else /* UDP */
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stw_be_p(tp->data+css+4, len);
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if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
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unsigned int phsum;
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@ -657,8 +660,10 @@ xmit_seg(E1000State *s)
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memmove(tp->data, tp->data + 4, 8);
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memcpy(tp->data + 8, tp->vlan_header, 4);
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e1000_send_packet(s, tp->vlan, tp->size + 4);
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} else
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} else {
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e1000_send_packet(s, tp->data, tp->size);
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}
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s->mac_reg[TPT]++;
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s->mac_reg[GPTC]++;
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n = s->mac_reg[TOTL];
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@ -679,7 +684,7 @@ process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
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struct e1000_tx *tp = &s->tx;
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s->mit_ide |= (txd_lower & E1000_TXD_CMD_IDE);
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if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor
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if (dtype == E1000_TXD_CMD_DEXT) { /* context descriptor */
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op = le32_to_cpu(xp->cmd_and_length);
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tp->ipcss = xp->lower_setup.ip_fields.ipcss;
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tp->ipcso = xp->lower_setup.ip_fields.ipcso;
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@ -694,7 +699,7 @@ process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
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tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0;
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tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0;
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tp->tso_frames = 0;
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if (tp->tucso == 0) { // this is probably wrong
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if (tp->tucso == 0) { /* this is probably wrong */
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DBGOUT(TXSUM, "TCP/UDP: cso 0!\n");
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tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
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}
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@ -1217,9 +1222,12 @@ static uint32_t (*macreg_readops[])(E1000State *, int) = {
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getreg(TDLEN), getreg(RDLEN), getreg(RDTR), getreg(RADV),
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getreg(TADV), getreg(ITR),
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[TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4,
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[GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4,
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[ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read,
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[TOTH] = mac_read_clr8, [TORH] = mac_read_clr8,
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[GPRC] = mac_read_clr4, [GPTC] = mac_read_clr4,
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[TPT] = mac_read_clr4, [TPR] = mac_read_clr4,
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[ICR] = mac_icr_read, [EECD] = get_eecd,
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[EERD] = flash_eerd_read,
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[CRCERRS ... MPC] = &mac_readreg,
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[RA ... RA+31] = &mac_readreg,
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[MTA ... MTA+127] = &mac_readreg,
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@ -1232,6 +1240,7 @@ static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
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putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
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putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
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putreg(RDBAL), putreg(LEDCTL), putreg(VET),
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[TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
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[TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
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[TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
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@ -1239,6 +1248,7 @@ static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
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[EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
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[RDTR] = set_16bit, [RADV] = set_16bit, [TADV] = set_16bit,
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[ITR] = set_16bit,
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[RA ... RA+31] = &mac_writereg,
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[MTA ... MTA+127] = &mac_writereg,
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[VFTA ... VFTA+127] = &mac_writereg,
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@ -158,7 +158,7 @@
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#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
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#define FEXTNVM_SW_CONFIG 0x0001
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#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
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#define E1000_PBS 0x01008 /* Packet Buffer Size */
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#define E1000_PBS 0x01008 /* Packet Buffer Size - RW */
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#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
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#define E1000_FLASH_UPDATES 1000
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#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
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