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target/arm: move cpu_tcg to tcg/cpu32.c 

move the module containing cpu models definitions
for 32bit TCG-only CPUs to tcg/ and rename it for clarity.

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230426180013.14814-8-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Claudio Fontana 2023-04-26 15:00:07 -03:00 committed by Peter Maydell
parent 557ed03a28
commit 20cf68efce
5 changed files with 5 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hw/arm/virt.c
View File

@ -206,9 +206,7 @@ static const int a15irqmap[] = {
static const char *valid_cpus[] = {
#ifdef CONFIG_TCG
ARM_CPU_TYPE_NAME("cortex-a7"),
#endif
ARM_CPU_TYPE_NAME("cortex-a15"),
#ifdef CONFIG_TCG
ARM_CPU_TYPE_NAME("cortex-a35"),
ARM_CPU_TYPE_NAME("cortex-a55"),
ARM_CPU_TYPE_NAME("cortex-a72"),

1
target/arm/meson.build
View File

@ -5,7 +5,6 @@ arm_ss.add(files(
'gdbstub.c',
'helper.c',
'vfp_helper.c',
'cpu_tcg.c',
))
arm_ss.add(zlib)

13
target/arm/cpu_tcg.c → target/arm/tcg/cpu32.c
View File

@ -1,5 +1,5 @@
/*
* QEMU ARM TCG CPUs.
* QEMU ARM TCG-only CPUs.
*
* Copyright (c) 2012 SUSE LINUX Products GmbH
*
@ -10,9 +10,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
#endif /* CONFIG_TCG */
#include "internals.h"
#include "target/arm/idau.h"
#if !defined(CONFIG_USER_ONLY)
@ -96,7 +94,7 @@ void aa32_max_features(ARMCPU *cpu)
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
#if !defined(CONFIG_USER_ONLY)
static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
CPUClass *cc = CPU_GET_CLASS(cs);
@ -120,7 +118,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
}
return ret;
}
#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
#endif /* !CONFIG_USER_ONLY */
static void arm926_initfn(Object *obj)
{
@ -1014,7 +1012,6 @@ static void pxa270c5_initfn(Object *obj)
cpu->reset_sctlr = 0x00000078;
}
#ifdef CONFIG_TCG
static const struct TCGCPUOps arm_v7m_tcg_ops = {
.initialize = arm_translate_init,
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
@ -1035,7 +1032,6 @@ static const struct TCGCPUOps arm_v7m_tcg_ops = {
.debug_check_breakpoint = arm_debug_check_breakpoint,
#endif /* !CONFIG_USER_ONLY */
};
#endif /* CONFIG_TCG */
static void arm_v7m_class_init(ObjectClass *oc, void *data)
{
@ -1043,10 +1039,7 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(oc);
acc->info = data;
#ifdef CONFIG_TCG
cc->tcg_ops = &arm_v7m_tcg_ops;
#endif /* CONFIG_TCG */
cc->gdb_core_xml_file = "arm-m-profile.xml";
}

2
target/arm/tcg/cpu64.c
View File

@ -525,7 +525,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
/*
* -cpu max: a CPU with as many features enabled as our emulation supports.
* The version of '-cpu max' for qemu-system-arm is defined in cpu_tcg.c;
* The version of '-cpu max' for qemu-system-arm is defined in cpu32.c;
* this only needs to handle 64 bits.
*/
void aarch64_max_tcg_initfn(Object *obj)

1
target/arm/tcg/meson.build
View File

@ -18,6 +18,7 @@ gen = [
arm_ss.add(gen)
arm_ss.add(files(
'cpu32.c',
'translate.c',
'translate-m-nocp.c',
'translate-mve.c',