mirror of https://github.com/xemu-project/xemu.git
target/arm: Wrap TCG-only code in debug_helper.c
The next few patches will move helpers under CONFIG_TCG. We'd prefer to keep the debug helpers and debug registers close together, so rearrange the file a bit to be able to wrap the helpers with a TCG ifdef. Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Fabiano Rosas
Peter Maydell
parent
fa05d1abb9
commit
2059ec754f
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@ -12,8 +12,9 @@
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#include "cpregs.h"
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#include "cpregs.h"
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#include "exec/exec-all.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "exec/helper-proto.h"
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#include "sysemu/tcg.h"
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#ifdef CONFIG_TCG
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/* Return the Exception Level targeted by debug exceptions. */
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/* Return the Exception Level targeted by debug exceptions. */
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static int arm_debug_target_el(CPUARMState *env)
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static int arm_debug_target_el(CPUARMState *env)
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{
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{
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@ -536,6 +537,243 @@ void HELPER(exception_swstep)(CPUARMState *env, uint32_t syndrome)
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raise_exception_debug(env, EXCP_UDEF, syndrome);
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raise_exception_debug(env, EXCP_UDEF, syndrome);
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}
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}
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void hw_watchpoint_update(ARMCPU *cpu, int n)
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{
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CPUARMState *env = &cpu->env;
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vaddr len = 0;
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vaddr wvr = env->cp15.dbgwvr[n];
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uint64_t wcr = env->cp15.dbgwcr[n];
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int mask;
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int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
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if (env->cpu_watchpoint[n]) {
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cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
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env->cpu_watchpoint[n] = NULL;
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}
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if (!FIELD_EX64(wcr, DBGWCR, E)) {
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/* E bit clear : watchpoint disabled */
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return;
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}
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switch (FIELD_EX64(wcr, DBGWCR, LSC)) {
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case 0:
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/* LSC 00 is reserved and must behave as if the wp is disabled */
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return;
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case 1:
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flags |= BP_MEM_READ;
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break;
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case 2:
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flags |= BP_MEM_WRITE;
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break;
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case 3:
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flags |= BP_MEM_ACCESS;
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break;
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}
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/*
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* Attempts to use both MASK and BAS fields simultaneously are
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* CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
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* thus generating a watchpoint for every byte in the masked region.
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*/
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mask = FIELD_EX64(wcr, DBGWCR, MASK);
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if (mask == 1 || mask == 2) {
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/*
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* Reserved values of MASK; we must act as if the mask value was
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* some non-reserved value, or as if the watchpoint were disabled.
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* We choose the latter.
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*/
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return;
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} else if (mask) {
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/* Watchpoint covers an aligned area up to 2GB in size */
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len = 1ULL << mask;
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/*
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* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
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* whether the watchpoint fires when the unmasked bits match; we opt
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* to generate the exceptions.
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*/
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wvr &= ~(len - 1);
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} else {
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/* Watchpoint covers bytes defined by the byte address select bits */
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int bas = FIELD_EX64(wcr, DBGWCR, BAS);
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int basstart;
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if (extract64(wvr, 2, 1)) {
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/*
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* Deprecated case of an only 4-aligned address. BAS[7:4] are
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* ignored, and BAS[3:0] define which bytes to watch.
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*/
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bas &= 0xf;
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}
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if (bas == 0) {
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/* This must act as if the watchpoint is disabled */
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return;
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}
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/*
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* The BAS bits are supposed to be programmed to indicate a contiguous
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* range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
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* we fire for each byte in the word/doubleword addressed by the WVR.
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* We choose to ignore any non-zero bits after the first range of 1s.
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*/
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basstart = ctz32(bas);
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len = cto32(bas >> basstart);
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wvr += basstart;
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}
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cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
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&env->cpu_watchpoint[n]);
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}
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void hw_watchpoint_update_all(ARMCPU *cpu)
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{
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int i;
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CPUARMState *env = &cpu->env;
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/*
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* Completely clear out existing QEMU watchpoints and our array, to
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* avoid possible stale entries following migration load.
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*/
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cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
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memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
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for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
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hw_watchpoint_update(cpu, i);
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}
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}
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void hw_breakpoint_update(ARMCPU *cpu, int n)
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{
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CPUARMState *env = &cpu->env;
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uint64_t bvr = env->cp15.dbgbvr[n];
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uint64_t bcr = env->cp15.dbgbcr[n];
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vaddr addr;
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int bt;
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int flags = BP_CPU;
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if (env->cpu_breakpoint[n]) {
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cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
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env->cpu_breakpoint[n] = NULL;
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}
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if (!extract64(bcr, 0, 1)) {
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/* E bit clear : watchpoint disabled */
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return;
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}
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bt = extract64(bcr, 20, 4);
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switch (bt) {
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case 4: /* unlinked address mismatch (reserved if AArch64) */
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case 5: /* linked address mismatch (reserved if AArch64) */
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qemu_log_mask(LOG_UNIMP,
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"arm: address mismatch breakpoint types not implemented\n");
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return;
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case 0: /* unlinked address match */
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case 1: /* linked address match */
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{
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/*
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* Bits [1:0] are RES0.
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*
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* It is IMPLEMENTATION DEFINED whether bits [63:49]
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* ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit
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* of the VA field ([48] or [52] for FEAT_LVA), or whether the
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* value is read as written. It is CONSTRAINED UNPREDICTABLE
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* whether the RESS bits are ignored when comparing an address.
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* Therefore we are allowed to compare the entire register, which
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* lets us avoid considering whether FEAT_LVA is actually enabled.
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*
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* The BAS field is used to allow setting breakpoints on 16-bit
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* wide instructions; it is CONSTRAINED UNPREDICTABLE whether
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* a bp will fire if the addresses covered by the bp and the addresses
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* covered by the insn overlap but the insn doesn't start at the
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* start of the bp address range. We choose to require the insn and
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* the bp to have the same address. The constraints on writing to
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* BAS enforced in dbgbcr_write mean we have only four cases:
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* 0b0000 => no breakpoint
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* 0b0011 => breakpoint on addr
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* 0b1100 => breakpoint on addr + 2
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* 0b1111 => breakpoint on addr
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* See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
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*/
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int bas = extract64(bcr, 5, 4);
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addr = bvr & ~3ULL;
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if (bas == 0) {
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return;
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}
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if (bas == 0xc) {
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addr += 2;
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}
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break;
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}
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case 2: /* unlinked context ID match */
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case 8: /* unlinked VMID match (reserved if no EL2) */
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case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
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qemu_log_mask(LOG_UNIMP,
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"arm: unlinked context breakpoint types not implemented\n");
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return;
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case 9: /* linked VMID match (reserved if no EL2) */
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case 11: /* linked context ID and VMID match (reserved if no EL2) */
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case 3: /* linked context ID match */
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default:
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/*
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* We must generate no events for Linked context matches (unless
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* they are linked to by some other bp/wp, which is handled in
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* updates for the linking bp/wp). We choose to also generate no events
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* for reserved values.
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*/
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return;
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}
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cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
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}
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void hw_breakpoint_update_all(ARMCPU *cpu)
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{
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int i;
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CPUARMState *env = &cpu->env;
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/*
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* Completely clear out existing QEMU breakpoints and our array, to
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* avoid possible stale entries following migration load.
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*/
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cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
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memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
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for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
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hw_breakpoint_update(cpu, i);
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}
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}
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#if !defined(CONFIG_USER_ONLY)
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vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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/*
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* In BE32 system mode, target memory is stored byteswapped (on a
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* little-endian host system), and by the time we reach here (via an
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* opcode helper) the addresses of subword accesses have been adjusted
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* to account for that, which means that watchpoints will not match.
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* Undo the adjustment here.
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*/
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if (arm_sctlr_b(env)) {
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if (len == 1) {
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addr ^= 3;
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} else if (len == 2) {
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addr ^= 2;
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}
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}
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return addr;
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}
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#endif /* !CONFIG_USER_ONLY */
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#endif /* CONFIG_TCG */
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/*
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/*
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* Check for traps to "powerdown debug" registers, which are controlled
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* Check for traps to "powerdown debug" registers, which are controlled
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* by MDCR.TDOSA
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* by MDCR.TDOSA
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@ -813,112 +1051,6 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
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.access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
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.access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
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};
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};
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void hw_watchpoint_update(ARMCPU *cpu, int n)
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{
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CPUARMState *env = &cpu->env;
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vaddr len = 0;
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vaddr wvr = env->cp15.dbgwvr[n];
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uint64_t wcr = env->cp15.dbgwcr[n];
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int mask;
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int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
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if (env->cpu_watchpoint[n]) {
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cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
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env->cpu_watchpoint[n] = NULL;
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}
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if (!FIELD_EX64(wcr, DBGWCR, E)) {
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/* E bit clear : watchpoint disabled */
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return;
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}
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switch (FIELD_EX64(wcr, DBGWCR, LSC)) {
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case 0:
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/* LSC 00 is reserved and must behave as if the wp is disabled */
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return;
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case 1:
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flags |= BP_MEM_READ;
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break;
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case 2:
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flags |= BP_MEM_WRITE;
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break;
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case 3:
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flags |= BP_MEM_ACCESS;
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break;
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}
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/*
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* Attempts to use both MASK and BAS fields simultaneously are
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* CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
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* thus generating a watchpoint for every byte in the masked region.
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*/
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mask = FIELD_EX64(wcr, DBGWCR, MASK);
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if (mask == 1 || mask == 2) {
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/*
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* Reserved values of MASK; we must act as if the mask value was
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* some non-reserved value, or as if the watchpoint were disabled.
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* We choose the latter.
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*/
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return;
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} else if (mask) {
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/* Watchpoint covers an aligned area up to 2GB in size */
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len = 1ULL << mask;
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/*
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* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
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* whether the watchpoint fires when the unmasked bits match; we opt
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* to generate the exceptions.
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*/
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wvr &= ~(len - 1);
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} else {
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/* Watchpoint covers bytes defined by the byte address select bits */
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int bas = FIELD_EX64(wcr, DBGWCR, BAS);
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int basstart;
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if (extract64(wvr, 2, 1)) {
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/*
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* Deprecated case of an only 4-aligned address. BAS[7:4] are
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|
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* ignored, and BAS[3:0] define which bytes to watch.
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*/
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bas &= 0xf;
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}
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if (bas == 0) {
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/* This must act as if the watchpoint is disabled */
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return;
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}
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|
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/*
|
|
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* The BAS bits are supposed to be programmed to indicate a contiguous
|
|
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* range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
|
|
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* we fire for each byte in the word/doubleword addressed by the WVR.
|
|
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* We choose to ignore any non-zero bits after the first range of 1s.
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*/
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basstart = ctz32(bas);
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len = cto32(bas >> basstart);
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wvr += basstart;
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}
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cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
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&env->cpu_watchpoint[n]);
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}
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|
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void hw_watchpoint_update_all(ARMCPU *cpu)
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|
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{
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|
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int i;
|
|
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CPUARMState *env = &cpu->env;
|
|
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|
|
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/*
|
|
||||||
* Completely clear out existing QEMU watchpoints and our array, to
|
|
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* avoid possible stale entries following migration load.
|
|
||||||
*/
|
|
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cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
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memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
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for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
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hw_watchpoint_update(cpu, i);
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}
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}
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static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
|
uint64_t value)
|
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{
|
{
|
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|
|
@ -956,109 +1088,6 @@ static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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}
|
}
|
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}
|
}
|
||||||
|
|
||||||
void hw_breakpoint_update(ARMCPU *cpu, int n)
|
|
||||||
{
|
|
||||||
CPUARMState *env = &cpu->env;
|
|
||||||
uint64_t bvr = env->cp15.dbgbvr[n];
|
|
||||||
uint64_t bcr = env->cp15.dbgbcr[n];
|
|
||||||
vaddr addr;
|
|
||||||
int bt;
|
|
||||||
int flags = BP_CPU;
|
|
||||||
|
|
||||||
if (env->cpu_breakpoint[n]) {
|
|
||||||
cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
|
|
||||||
env->cpu_breakpoint[n] = NULL;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!extract64(bcr, 0, 1)) {
|
|
||||||
/* E bit clear : watchpoint disabled */
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
bt = extract64(bcr, 20, 4);
|
|
||||||
|
|
||||||
switch (bt) {
|
|
||||||
case 4: /* unlinked address mismatch (reserved if AArch64) */
|
|
||||||
case 5: /* linked address mismatch (reserved if AArch64) */
|
|
||||||
qemu_log_mask(LOG_UNIMP,
|
|
||||||
"arm: address mismatch breakpoint types not implemented\n");
|
|
||||||
return;
|
|
||||||
case 0: /* unlinked address match */
|
|
||||||
case 1: /* linked address match */
|
|
||||||
{
|
|
||||||
/*
|
|
||||||
* Bits [1:0] are RES0.
|
|
||||||
*
|
|
||||||
* It is IMPLEMENTATION DEFINED whether bits [63:49]
|
|
||||||
* ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit
|
|
||||||
* of the VA field ([48] or [52] for FEAT_LVA), or whether the
|
|
||||||
* value is read as written. It is CONSTRAINED UNPREDICTABLE
|
|
||||||
* whether the RESS bits are ignored when comparing an address.
|
|
||||||
* Therefore we are allowed to compare the entire register, which
|
|
||||||
* lets us avoid considering whether FEAT_LVA is actually enabled.
|
|
||||||
*
|
|
||||||
* The BAS field is used to allow setting breakpoints on 16-bit
|
|
||||||
* wide instructions; it is CONSTRAINED UNPREDICTABLE whether
|
|
||||||
* a bp will fire if the addresses covered by the bp and the addresses
|
|
||||||
* covered by the insn overlap but the insn doesn't start at the
|
|
||||||
* start of the bp address range. We choose to require the insn and
|
|
||||||
* the bp to have the same address. The constraints on writing to
|
|
||||||
* BAS enforced in dbgbcr_write mean we have only four cases:
|
|
||||||
* 0b0000 => no breakpoint
|
|
||||||
* 0b0011 => breakpoint on addr
|
|
||||||
* 0b1100 => breakpoint on addr + 2
|
|
||||||
* 0b1111 => breakpoint on addr
|
|
||||||
* See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
|
|
||||||
*/
|
|
||||||
int bas = extract64(bcr, 5, 4);
|
|
||||||
addr = bvr & ~3ULL;
|
|
||||||
if (bas == 0) {
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
if (bas == 0xc) {
|
|
||||||
addr += 2;
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
case 2: /* unlinked context ID match */
|
|
||||||
case 8: /* unlinked VMID match (reserved if no EL2) */
|
|
||||||
case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
|
|
||||||
qemu_log_mask(LOG_UNIMP,
|
|
||||||
"arm: unlinked context breakpoint types not implemented\n");
|
|
||||||
return;
|
|
||||||
case 9: /* linked VMID match (reserved if no EL2) */
|
|
||||||
case 11: /* linked context ID and VMID match (reserved if no EL2) */
|
|
||||||
case 3: /* linked context ID match */
|
|
||||||
default:
|
|
||||||
/*
|
|
||||||
* We must generate no events for Linked context matches (unless
|
|
||||||
* they are linked to by some other bp/wp, which is handled in
|
|
||||||
* updates for the linking bp/wp). We choose to also generate no events
|
|
||||||
* for reserved values.
|
|
||||||
*/
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
|
|
||||||
}
|
|
||||||
|
|
||||||
void hw_breakpoint_update_all(ARMCPU *cpu)
|
|
||||||
{
|
|
||||||
int i;
|
|
||||||
CPUARMState *env = &cpu->env;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Completely clear out existing QEMU breakpoints and our array, to
|
|
||||||
* avoid possible stale entries following migration load.
|
|
||||||
*/
|
|
||||||
cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
|
|
||||||
memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
|
|
||||||
|
|
||||||
for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
|
|
||||||
hw_breakpoint_update(cpu, i);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||||
uint64_t value)
|
uint64_t value)
|
||||||
{
|
{
|
||||||
|
|
@ -1210,30 +1239,3 @@ void define_debug_regs(ARMCPU *cpu)
|
||||||
g_free(dbgwcr_el1_name);
|
g_free(dbgwcr_el1_name);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
#if !defined(CONFIG_USER_ONLY)
|
|
||||||
|
|
||||||
vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
|
|
||||||
{
|
|
||||||
ARMCPU *cpu = ARM_CPU(cs);
|
|
||||||
CPUARMState *env = &cpu->env;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* In BE32 system mode, target memory is stored byteswapped (on a
|
|
||||||
* little-endian host system), and by the time we reach here (via an
|
|
||||||
* opcode helper) the addresses of subword accesses have been adjusted
|
|
||||||
* to account for that, which means that watchpoints will not match.
|
|
||||||
* Undo the adjustment here.
|
|
||||||
*/
|
|
||||||
if (arm_sctlr_b(env)) {
|
|
||||||
if (len == 1) {
|
|
||||||
addr ^= 3;
|
|
||||||
} else if (len == 2) {
|
|
||||||
addr ^= 2;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return addr;
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue