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Add the ability to change the FEC PHY MDIO devices numbers on i.MX7 processor 

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: c850187322be9930e47c8b234c385a7d0da245cb.1593806826.git.jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: updated for object_property_set_uint() argument reordering]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Jean-Christophe Dubois 2020-07-13 14:36:08 +01:00 committed by Peter Maydell
parent a9c167a3c4
commit 1f7197deb0
2 changed files with 10 additions and 0 deletions
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9
hw/arm/fsl-imx7.c
View File

@ -363,6 +363,8 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
FSL_IMX7_ENET2_ADDR, FSL_IMX7_ENET2_ADDR,
}; };
object_property_set_uint(OBJECT(&s->eth[i]), "phy-num",
s->phy_num[i], &error_abort);
object_property_set_uint(OBJECT(&s->eth[i]), "tx-ring-num", object_property_set_uint(OBJECT(&s->eth[i]), "tx-ring-num",
FSL_IMX7_ETH_NUM_TX_RINGS, &error_abort); FSL_IMX7_ETH_NUM_TX_RINGS, &error_abort);
qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]); qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]);
@ -550,10 +552,17 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
FSL_IMX7_PCIE_PHY_SIZE); FSL_IMX7_PCIE_PHY_SIZE);
} }
static Property fsl_imx7_properties[] = {
DEFINE_PROP_UINT32("fec1-phy-num", FslIMX7State, phy_num[0], 0),
DEFINE_PROP_UINT32("fec2-phy-num", FslIMX7State, phy_num[1], 1),
DEFINE_PROP_END_OF_LIST(),
};
static void fsl_imx7_class_init(ObjectClass *oc, void *data) static void fsl_imx7_class_init(ObjectClass *oc, void *data)
{ {
DeviceClass *dc = DEVICE_CLASS(oc); DeviceClass *dc = DEVICE_CLASS(oc);
device_class_set_props(dc, fsl_imx7_properties);
dc->realize = fsl_imx7_realize; dc->realize = fsl_imx7_realize;
/* Reason: Uses serial_hds and nd_table in realize() directly */ /* Reason: Uses serial_hds and nd_table in realize() directly */

1
include/hw/arm/fsl-imx7.h
View File

@ -81,6 +81,7 @@ typedef struct FslIMX7State {
IMX7GPRState gpr; IMX7GPRState gpr;
ChipideaState usb[FSL_IMX7_NUM_USBS]; ChipideaState usb[FSL_IMX7_NUM_USBS];
DesignwarePCIEHost pcie; DesignwarePCIEHost pcie;
uint32_t phy_num[FSL_IMX7_NUM_ETHS];
} FslIMX7State; } FslIMX7State;
enum FslIMX7MemoryMap { enum FslIMX7MemoryMap {