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target/i386: Introduce REX_PREFIX 

The existing flag, x86_64_hregs, does not accurately describe
its setting.  It is true if and only if a REX prefix has been
seen.  Yes, that affects the "h" regs, but that's secondary.

Add PREFIX_REX and include this bit in s->prefix.  Add REX_PREFIX
so that the check folds away when x86_64 is compiled out.

Fold away the reg >= 8 check, because bit 3 of the register
number comes from the REX prefix in the first place.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20210514151342.384376-16-richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2021-05-14 10:13:07 -05:00
parent beedb93c04
commit 1e92b7275c
1 changed files with 11 additions and 18 deletions
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29
target/i386/tcg/translate.c
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@ -39,6 +39,7 @@
#define PREFIX_DATA 0x08 #define PREFIX_DATA 0x08
#define PREFIX_ADR 0x10 #define PREFIX_ADR 0x10
#define PREFIX_VEX 0x20 #define PREFIX_VEX 0x20
#define PREFIX_REX 0x40
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
#define REX_X(s) ((s)->rex_x) #define REX_X(s) ((s)->rex_x)
@ -105,9 +106,6 @@ typedef struct DisasContext {
int vex_v; /* vex vvvv register, without 1's complement. */ int vex_v; /* vex vvvv register, without 1's complement. */
CCOp cc_op; /* current CC operation */ CCOp cc_op; /* current CC operation */
bool cc_op_dirty; bool cc_op_dirty;
#ifdef TARGET_X86_64
bool x86_64_hregs;
#endif
int f_st; /* currently unused */ int f_st; /* currently unused */
int tf; /* TF cpu flag */ int tf; /* TF cpu flag */
int jmp_opt; /* use direct block chaining for direct jumps */ int jmp_opt; /* use direct block chaining for direct jumps */
@ -173,6 +171,12 @@ typedef struct DisasContext {
#define LMA(S) (((S)->flags & HF_LMA_MASK) != 0) #define LMA(S) (((S)->flags & HF_LMA_MASK) != 0)
#endif #endif
#ifdef TARGET_X86_64
#define REX_PREFIX(S) (((S)->prefix & PREFIX_REX) != 0)
#else
#define REX_PREFIX(S) false
#endif
static void gen_eob(DisasContext *s); static void gen_eob(DisasContext *s);
static void gen_jr(DisasContext *s, TCGv dest); static void gen_jr(DisasContext *s, TCGv dest);
static void gen_jmp(DisasContext *s, target_ulong eip); static void gen_jmp(DisasContext *s, target_ulong eip);
@ -336,14 +340,10 @@ static void gen_update_cc_op(DisasContext *s)
*/ */
static inline bool byte_reg_is_xH(DisasContext *s, int reg) static inline bool byte_reg_is_xH(DisasContext *s, int reg)
{ {
if (reg < 4) { /* Any time the REX prefix is present, byte registers are uniform */
if (reg < 4 || REX_PREFIX(s)) {
return false; return false;
} }
#ifdef TARGET_X86_64
if (reg >= 8 || s->x86_64_hregs) {
return false;
}
#endif
return true; return true;
} }
@ -4559,7 +4559,6 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
s->rex_x = 0; s->rex_x = 0;
s->rex_b = 0; s->rex_b = 0;
s->x86_64_hregs = false;
#endif #endif
s->rip_offset = 0; /* for relative ip address */ s->rip_offset = 0; /* for relative ip address */
s->vex_l = 0; s->vex_l = 0;
@ -4614,12 +4613,11 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
case 0x40 ... 0x4f: case 0x40 ... 0x4f:
if (CODE64(s)) { if (CODE64(s)) {
/* REX prefix */ /* REX prefix */
prefixes |= PREFIX_REX;
rex_w = (b >> 3) & 1; rex_w = (b >> 3) & 1;
rex_r = (b & 0x4) << 1; rex_r = (b & 0x4) << 1;
s->rex_x = (b & 0x2) << 2; s->rex_x = (b & 0x2) << 2;
REX_B(s) = (b & 0x1) << 3; REX_B(s) = (b & 0x1) << 3;
/* select uniform byte register addressing */
s->x86_64_hregs = true;
goto next_byte; goto next_byte;
} }
break; break;
@ -4643,14 +4641,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
/* 4.1.1-4.1.3: No preceding lock, 66, f2, f3, or rex prefixes. */ /* 4.1.1-4.1.3: No preceding lock, 66, f2, f3, or rex prefixes. */
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ
| PREFIX_LOCK | PREFIX_DATA)) { | PREFIX_LOCK | PREFIX_DATA | PREFIX_REX)) {
goto illegal_op; goto illegal_op;
} }
#ifdef TARGET_X86_64
if (s->x86_64_hregs) {
goto illegal_op;
}
#endif
rex_r = (~vex2 >> 4) & 8; rex_r = (~vex2 >> 4) & 8;
if (b == 0xc5) { if (b == 0xc5) {
/* 2-byte VEX prefix: RVVVVlpp, implied 0f leading opcode byte */ /* 2-byte VEX prefix: RVVVVlpp, implied 0f leading opcode byte */