From 1e5a7c57a577d7702c668ef9fcdc9fa4187ef8aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Wed, 14 Aug 2024 11:14:49 +0200 Subject: [PATCH] linux-user/mips: Select Octeon68XX CPU for Octeon binaries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Octeon68XX CPU is available since commit 9a6046a655 ("target/mips: introduce Cavium Octeon CPU model"). Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1722 Reported-by: Johnathan Hữu Trí Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240814133928.6746-3-philmd@linaro.org> --- linux-user/mips64/target_elf.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/linux-user/mips64/target_elf.h b/linux-user/mips64/target_elf.h index ec55d8542a..ce6fb6541e 100644 --- a/linux-user/mips64/target_elf.h +++ b/linux-user/mips64/target_elf.h @@ -9,6 +9,14 @@ #define MIPS64_TARGET_ELF_H static inline const char *cpu_get_model(uint32_t eflags) { + switch (eflags & EF_MIPS_MACH) { + case EF_MIPS_MACH_OCTEON: + case EF_MIPS_MACH_OCTEON2: + case EF_MIPS_MACH_OCTEON3: + return "Octeon68XX"; + default: + break; + } if ((eflags & EF_MIPS_ARCH) == EF_MIPS_ARCH_64R6) { return "I6400"; }