diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index 009dc96dbd..321885f951 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -171,7 +171,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond) } else { tcg_gen_brcond_tl(cond, src1, src2, l); } - gen_goto_tb(ctx, 1, ctx->pc_succ_insn); + gen_goto_tb(ctx, 1, ctx->cur_insn_len); gen_set_label(l); /* branch taken */ @@ -183,7 +183,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond) gen_pc_plus_diff(target_pc, ctx, next_pc); gen_exception_inst_addr_mis(ctx, target_pc); } else { - gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm); + gen_goto_tb(ctx, 0, a->imm); } ctx->base.is_jmp = DISAS_NORETURN; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ea63d20eef..33c666d74e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -283,8 +283,10 @@ static void exit_tb(DisasContext *ctx) tcg_gen_exit_tb(NULL, 0); } -static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) +static void gen_goto_tb(DisasContext *ctx, int n, target_long diff) { + target_ulong dest = ctx->base.pc_next + diff; + /* * Under itrigger, instruction executes one by one like singlestep, * direct block chain benefits will be small. @@ -559,7 +561,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) } gen_set_gpri(ctx, rd, ctx->pc_succ_insn); - gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ + gen_goto_tb(ctx, 0, imm); /* must use this for safety */ ctx->base.is_jmp = DISAS_NORETURN; } @@ -1231,7 +1233,7 @@ static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) switch (ctx->base.is_jmp) { case DISAS_TOO_MANY: - gen_goto_tb(ctx, 0, ctx->base.pc_next); + gen_goto_tb(ctx, 0, 0); break; case DISAS_NORETURN: break;