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target/arm: Move stage_1_mmu_idx, arm_stage1_mmu_idx to ptw.c 

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-28-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-06-08 19:38:54 +01:00 committed by Peter Maydell
parent 23971205cf
commit 1d26125536
2 changed files with 28 additions and 32 deletions
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32
target/arm/helper.c
View File

@ -10427,31 +10427,6 @@ uint64_t arm_sctlr(CPUARMState *env, int el)
return env->cp15.sctlr_el[el]; return env->cp15.sctlr_el[el];
} }
#ifndef CONFIG_USER_ONLY
/* Convert a possible stage1+2 MMU index into the appropriate
* stage 1 MMU index
*/
ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
{
switch (mmu_idx) {
case ARMMMUIdx_SE10_0:
return ARMMMUIdx_Stage1_SE0;
case ARMMMUIdx_SE10_1:
return ARMMMUIdx_Stage1_SE1;
case ARMMMUIdx_SE10_1_PAN:
return ARMMMUIdx_Stage1_SE1_PAN;
case ARMMMUIdx_E10_0:
return ARMMMUIdx_Stage1_E0;
case ARMMMUIdx_E10_1:
return ARMMMUIdx_Stage1_E1;
case ARMMMUIdx_E10_1_PAN:
return ARMMMUIdx_Stage1_E1_PAN;
default:
return mmu_idx;
}
}
#endif /* !CONFIG_USER_ONLY */
int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx)
{ {
if (regime_has_2_ranges(mmu_idx)) { if (regime_has_2_ranges(mmu_idx)) {
@ -11081,13 +11056,6 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env)
return arm_mmu_idx_el(env, arm_current_el(env)); return arm_mmu_idx_el(env, arm_current_el(env));
} }
#ifndef CONFIG_USER_ONLY
ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env)
{
return stage_1_mmu_idx(arm_mmu_idx(env));
}
#endif
static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
ARMMMUIdx mmu_idx, ARMMMUIdx mmu_idx,
CPUARMTBFlags flags) CPUARMTBFlags flags)

28
target/arm/ptw.c
View File

@ -47,6 +47,34 @@ unsigned int arm_pamax(ARMCPU *cpu)
return pamax_map[parange]; return pamax_map[parange];
} }
/*
* Convert a possible stage1+2 MMU index into the appropriate stage 1 MMU index
*/
ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
{
switch (mmu_idx) {
case ARMMMUIdx_SE10_0:
return ARMMMUIdx_Stage1_SE0;
case ARMMMUIdx_SE10_1:
return ARMMMUIdx_Stage1_SE1;
case ARMMMUIdx_SE10_1_PAN:
return ARMMMUIdx_Stage1_SE1_PAN;
case ARMMMUIdx_E10_0:
return ARMMMUIdx_Stage1_E0;
case ARMMMUIdx_E10_1:
return ARMMMUIdx_Stage1_E1;
case ARMMMUIdx_E10_1_PAN:
return ARMMMUIdx_Stage1_E1_PAN;
default:
return mmu_idx;
}
}
ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env)
{
return stage_1_mmu_idx(arm_mmu_idx(env));
}
static bool regime_translation_big_endian(CPUARMState *env, ARMMMUIdx mmu_idx) static bool regime_translation_big_endian(CPUARMState *env, ARMMMUIdx mmu_idx)
{ {
return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0;