mirror of https://github.com/xemu-project/xemu.git
dp8393x: checkpatch fixes
Also fix a simple comment typo of "constrainst" to "constraints". Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Finn Thain <fthain@linux-m68k.org> Message-Id: <20210625065401.30170-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Mark Cave-Ayland
Philippe Mathieu-Daudé
parent
8660df5ea2
commit
1ca82a8db0
hw/net
231
hw/net/dp8393x.c
231
hw/net/dp8393x.c
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@ -29,14 +29,14 @@
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#include <zlib.h>
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#include "qom/object.h"
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//#define DEBUG_SONIC
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/* #define DEBUG_SONIC */
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#define SONIC_PROM_SIZE 0x1000
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#ifdef DEBUG_SONIC
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#define DPRINTF(fmt, ...) \
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do { printf("sonic: " fmt , ## __VA_ARGS__); } while (0)
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static const char* reg_names[] = {
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static const char *reg_names[] = {
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"CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA",
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"TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0",
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"CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP",
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@ -185,7 +185,8 @@ struct dp8393xState {
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AddressSpace as;
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};
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/* Accessor functions for values which are formed by
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/*
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* Accessor functions for values which are formed by
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* concatenating two 16 bit device registers. By putting these
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* in their own functions with a uint32_t return type we avoid the
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* pitfall of implicit sign extension where ((x << 16) | y) is a
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@ -350,8 +351,7 @@ static void dp8393x_do_read_rra(dp8393xState *s)
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}
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/* Warn the host if CRBA now has the last available resource */
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if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP])
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{
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if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) {
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s->regs[SONIC_ISR] |= SONIC_ISR_RBE;
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dp8393x_update_irq(s);
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}
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@ -364,7 +364,8 @@ static void dp8393x_do_software_reset(dp8393xState *s)
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{
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timer_del(s->watchdog);
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s->regs[SONIC_CR] &= ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP | SONIC_CR_HTX);
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s->regs[SONIC_CR] &= ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP |
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SONIC_CR_HTX);
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s->regs[SONIC_CR] |= SONIC_CR_RST | SONIC_CR_RXDIS;
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}
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@ -490,8 +491,10 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
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/* Handle Ethernet checksum */
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if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) {
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/* Don't append FCS there, to look like slirp packets
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* which don't have one */
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/*
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* Don't append FCS there, to look like slirp packets
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* which don't have one
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*/
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} else {
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/* Remove existing FCS */
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tx_len -= 4;
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@ -558,26 +561,34 @@ static void dp8393x_do_command(dp8393xState *s, uint16_t command)
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s->regs[SONIC_CR] |= (command & SONIC_CR_MASK);
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if (command & SONIC_CR_HTX)
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if (command & SONIC_CR_HTX) {
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dp8393x_do_halt_transmission(s);
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if (command & SONIC_CR_TXP)
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}
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if (command & SONIC_CR_TXP) {
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dp8393x_do_transmit_packets(s);
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if (command & SONIC_CR_RXDIS)
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}
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if (command & SONIC_CR_RXDIS) {
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dp8393x_do_receiver_disable(s);
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if (command & SONIC_CR_RXEN)
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}
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if (command & SONIC_CR_RXEN) {
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dp8393x_do_receiver_enable(s);
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if (command & SONIC_CR_STP)
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}
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if (command & SONIC_CR_STP) {
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dp8393x_do_stop_timer(s);
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if (command & SONIC_CR_ST)
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}
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if (command & SONIC_CR_ST) {
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dp8393x_do_start_timer(s);
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if (command & SONIC_CR_RST)
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}
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if (command & SONIC_CR_RST) {
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dp8393x_do_software_reset(s);
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}
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if (command & SONIC_CR_RRRA) {
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dp8393x_do_read_rra(s);
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s->regs[SONIC_CR] &= ~SONIC_CR_RRRA;
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}
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if (command & SONIC_CR_LCAM)
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if (command & SONIC_CR_LCAM) {
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dp8393x_do_load_cam(s);
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}
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}
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static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size)
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@ -587,24 +598,24 @@ static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size)
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uint16_t val = 0;
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switch (reg) {
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/* Update data before reading it */
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case SONIC_WT0:
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case SONIC_WT1:
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dp8393x_update_wt_regs(s);
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val = s->regs[reg];
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break;
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/* Accept read to some registers only when in reset mode */
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case SONIC_CAP2:
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case SONIC_CAP1:
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case SONIC_CAP0:
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if (s->regs[SONIC_CR] & SONIC_CR_RST) {
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val = s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg) + 1] << 8;
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val |= s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg)];
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}
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break;
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/* All other registers have no special contrainst */
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default:
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val = s->regs[reg];
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/* Update data before reading it */
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case SONIC_WT0:
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case SONIC_WT1:
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dp8393x_update_wt_regs(s);
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val = s->regs[reg];
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break;
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/* Accept read to some registers only when in reset mode */
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case SONIC_CAP2:
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case SONIC_CAP1:
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case SONIC_CAP0:
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if (s->regs[SONIC_CR] & SONIC_CR_RST) {
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val = s->cam[s->regs[SONIC_CEP] & 0xf][2 * (SONIC_CAP0 - reg) + 1] << 8;
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val |= s->cam[s->regs[SONIC_CEP] & 0xf][2 * (SONIC_CAP0 - reg)];
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}
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break;
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/* All other registers have no special contraints */
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default:
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val = s->regs[reg];
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}
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DPRINTF("read 0x%04x from reg %s\n", val, reg_names[reg]);
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@ -622,75 +633,75 @@ static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data,
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DPRINTF("write 0x%04x to reg %s\n", (uint16_t)val, reg_names[reg]);
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switch (reg) {
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/* Command register */
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case SONIC_CR:
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dp8393x_do_command(s, val);
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break;
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/* Prevent write to read-only registers */
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case SONIC_CAP2:
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case SONIC_CAP1:
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case SONIC_CAP0:
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case SONIC_SR:
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case SONIC_MDT:
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DPRINTF("writing to reg %d invalid\n", reg);
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break;
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/* Accept write to some registers only when in reset mode */
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case SONIC_DCR:
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if (s->regs[SONIC_CR] & SONIC_CR_RST) {
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s->regs[reg] = val & 0xbfff;
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} else {
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DPRINTF("writing to DCR invalid\n");
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}
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break;
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case SONIC_DCR2:
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if (s->regs[SONIC_CR] & SONIC_CR_RST) {
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s->regs[reg] = val & 0xf017;
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} else {
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DPRINTF("writing to DCR2 invalid\n");
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}
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break;
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/* 12 lower bytes are Read Only */
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case SONIC_TCR:
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s->regs[reg] = val & 0xf000;
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break;
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/* 9 lower bytes are Read Only */
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case SONIC_RCR:
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s->regs[reg] = val & 0xffe0;
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break;
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/* Ignore most significant bit */
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case SONIC_IMR:
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s->regs[reg] = val & 0x7fff;
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dp8393x_update_irq(s);
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break;
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/* Clear bits by writing 1 to them */
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case SONIC_ISR:
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val &= s->regs[reg];
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s->regs[reg] &= ~val;
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if (val & SONIC_ISR_RBE) {
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dp8393x_do_read_rra(s);
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}
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dp8393x_update_irq(s);
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break;
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/* The guest is required to store aligned pointers here */
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case SONIC_RSA:
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case SONIC_REA:
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case SONIC_RRP:
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case SONIC_RWP:
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if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {
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s->regs[reg] = val & 0xfffc;
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} else {
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s->regs[reg] = val & 0xfffe;
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}
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break;
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/* Invert written value for some registers */
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case SONIC_CRCT:
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case SONIC_FAET:
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case SONIC_MPT:
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s->regs[reg] = val ^ 0xffff;
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break;
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/* All other registers have no special contrainst */
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default:
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s->regs[reg] = val;
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/* Command register */
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case SONIC_CR:
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dp8393x_do_command(s, val);
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break;
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/* Prevent write to read-only registers */
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case SONIC_CAP2:
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case SONIC_CAP1:
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case SONIC_CAP0:
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case SONIC_SR:
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case SONIC_MDT:
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DPRINTF("writing to reg %d invalid\n", reg);
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break;
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/* Accept write to some registers only when in reset mode */
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case SONIC_DCR:
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if (s->regs[SONIC_CR] & SONIC_CR_RST) {
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s->regs[reg] = val & 0xbfff;
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} else {
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DPRINTF("writing to DCR invalid\n");
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}
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break;
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case SONIC_DCR2:
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if (s->regs[SONIC_CR] & SONIC_CR_RST) {
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s->regs[reg] = val & 0xf017;
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} else {
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DPRINTF("writing to DCR2 invalid\n");
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}
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break;
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/* 12 lower bytes are Read Only */
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case SONIC_TCR:
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s->regs[reg] = val & 0xf000;
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break;
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/* 9 lower bytes are Read Only */
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case SONIC_RCR:
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s->regs[reg] = val & 0xffe0;
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break;
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/* Ignore most significant bit */
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case SONIC_IMR:
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s->regs[reg] = val & 0x7fff;
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dp8393x_update_irq(s);
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break;
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/* Clear bits by writing 1 to them */
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case SONIC_ISR:
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val &= s->regs[reg];
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s->regs[reg] &= ~val;
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if (val & SONIC_ISR_RBE) {
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dp8393x_do_read_rra(s);
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}
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dp8393x_update_irq(s);
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break;
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/* The guest is required to store aligned pointers here */
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case SONIC_RSA:
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case SONIC_REA:
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case SONIC_RRP:
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case SONIC_RWP:
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if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {
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s->regs[reg] = val & 0xfffc;
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} else {
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s->regs[reg] = val & 0xfffe;
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}
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break;
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/* Invert written value for some registers */
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case SONIC_CRCT:
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case SONIC_FAET:
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case SONIC_MPT:
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s->regs[reg] = val ^ 0xffff;
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break;
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/* All other registers have no special contrainst */
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default:
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s->regs[reg] = val;
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}
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if (reg == SONIC_WT0 || reg == SONIC_WT1) {
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@ -747,17 +758,18 @@ static int dp8393x_receive_filter(dp8393xState *s, const uint8_t * buf,
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}
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/* Check broadcast */
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if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) && !memcmp(buf, bcast, sizeof(bcast))) {
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if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) &&
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!memcmp(buf, bcast, sizeof(bcast))) {
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return SONIC_RCR_BC;
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}
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/* Check CAM */
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for (i = 0; i < 16; i++) {
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if (s->regs[SONIC_CE] & (1 << i)) {
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/* Entry enabled */
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if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) {
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return 0;
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}
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/* Entry enabled */
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if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) {
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return 0;
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}
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}
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}
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@ -938,7 +950,8 @@ static void dp8393x_reset(DeviceState *dev)
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s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux/mips */
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s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS;
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s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR);
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s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD | SONIC_RCR_RNT);
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s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD |
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SONIC_RCR_RNT);
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s->regs[SONIC_TCR] |= SONIC_TCR_NCRS | SONIC_TCR_PTX;
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s->regs[SONIC_TCR] &= ~SONIC_TCR_BCM;
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s->regs[SONIC_IMR] = 0;
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