From 1c6b2e4b794d460a16a7f94cf6a7d6864f708be1 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Thu, 2 Feb 2023 13:04:25 +0100 Subject: [PATCH] target/tricore: Fix OPC2_32_RCRW_INSERT translation we were mixing up the "c" and "d" registers. We used "d" as a destination register und "c" as the source. According to the TriCore ISA manual 1.6 vol 2 it is the other way round. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Resolves: https://gitlab.com/qemu-project/qemu/-/issues/653 Message-Id: <20230202120432.1268-4-kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann --- target/tricore/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 8de4e56b1f..6149d4f5c0 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -5805,8 +5805,8 @@ static void decode_rcrw_insert(DisasContext *ctx) tcg_gen_movi_tl(temp, width); tcg_gen_movi_tl(temp2, const4); - tcg_gen_andi_tl(temp3, cpu_gpr_d[r4], 0x1f); - gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp2, temp, temp3); + tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f); + gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], temp2, temp, temp3); tcg_temp_free(temp3); break;