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target-mips: fix {RD, WR}PGPR in microMIPS 

rt, rs were swapped

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
This commit is contained in:
Yongbok Kim 2015-06-25 00:24:13 +01:00 committed by Leon Alrae
parent 2c44b19c19
commit 1bf5902de0
1 changed files with 2 additions and 2 deletions
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4
target-mips/translate.c
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@ -13001,12 +13001,12 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
case RDPGPR:
check_cp0_enabled(ctx);
check_insn(ctx, ISA_MIPS32R2);
gen_load_srsgpr(rt, rs);
gen_load_srsgpr(rs, rt);
break;
case WRPGPR:
check_cp0_enabled(ctx);
check_insn(ctx, ISA_MIPS32R2);
gen_store_srsgpr(rt, rs);
gen_store_srsgpr(rs, rt);
break;
default:
goto pool32axf_invalid;