Rename cpu_reset() to cpu_state_reset()

Frees the identifier cpu_reset for QOM CPUs (manual rename).

Don't hide the parameter type behind explicit casts, use static
functions with strongly typed argument to indirect.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Andreas Färber 2012-02-08 03:03:33 +01:00
parent fc0b2c0f1a
commit 1bba0dc932
48 changed files with 98 additions and 61 deletions

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@ -917,7 +917,7 @@ int main(int argc, char **argv)
exit(1); exit(1);
} }
#if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC) #if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC)
cpu_reset(env); cpu_state_reset(env);
#endif #endif
thread_env = env; thread_env = env;

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@ -433,7 +433,7 @@ void cpu_watchpoint_remove_all(CPUState *env, int mask);
#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
void cpu_single_step(CPUState *env, int enabled); void cpu_single_step(CPUState *env, int enabled);
void cpu_reset(CPUState *s); void cpu_state_reset(CPUState *s);
int cpu_is_stopped(CPUState *env); int cpu_is_stopped(CPUState *env);
void run_on_cpu(CPUState *env, void (*func)(void *data), void *data); void run_on_cpu(CPUState *env, void (*func)(void *data), void *data);

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@ -340,7 +340,7 @@ int cpu_exec(CPUState *env)
} }
#elif defined(TARGET_PPC) #elif defined(TARGET_PPC)
if ((interrupt_request & CPU_INTERRUPT_RESET)) { if ((interrupt_request & CPU_INTERRUPT_RESET)) {
cpu_reset(env); cpu_state_reset(env);
} }
if (interrupt_request & CPU_INTERRUPT_HARD) { if (interrupt_request & CPU_INTERRUPT_HARD) {
ppc_hw_interrupt(env); ppc_hw_interrupt(env);

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@ -858,7 +858,7 @@ int main(int argc, char **argv)
/* NOTE: we need to init the CPU at this stage to get /* NOTE: we need to init the CPU at this stage to get
qemu_host_page_size */ qemu_host_page_size */
env = cpu_init(cpu_model); env = cpu_init(cpu_model);
cpu_reset(env); cpu_state_reset(env);
printf("Starting %s with qemu\n----------------\n", filename); printf("Starting %s with qemu\n----------------\n", filename);

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@ -277,7 +277,7 @@ static void do_cpu_reset(void *opaque)
CPUState *env = opaque; CPUState *env = opaque;
const struct arm_boot_info *info = env->boot_info; const struct arm_boot_info *info = env->boot_info;
cpu_reset(env); cpu_state_reset(env);
if (info) { if (info) {
if (!info->is_linux) { if (!info->is_linux) {
/* Jump to the entry point. */ /* Jump to the entry point. */

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@ -149,7 +149,7 @@ static void armv7m_bitband_init(void)
static void armv7m_reset(void *opaque) static void armv7m_reset(void *opaque)
{ {
cpu_reset((CPUState *)opaque); cpu_state_reset((CPUState *)opaque);
} }
/* Init CPU and memory for a v7-M based board. /* Init CPU and memory for a v7-M based board.

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@ -34,7 +34,7 @@ static void main_cpu_reset(void *opaque)
li = env->load_info; li = env->load_info;
cpu_reset(env); cpu_state_reset(env);
if (!li) { if (!li) {
/* nothing more to do. */ /* nothing more to do. */

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@ -51,7 +51,7 @@ static void main_cpu_reset(void *opaque)
ResetData *s = (ResetData *)opaque; ResetData *s = (ResetData *)opaque;
CPUState *env = s->env; CPUState *env = s->env;
cpu_reset(env); cpu_state_reset(env);
env->halted = 0; env->halted = 0;
env->pc = s->entry; env->pc = s->entry;

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@ -56,7 +56,7 @@ static void main_cpu_reset(void *opaque)
ResetInfo *reset_info = opaque; ResetInfo *reset_info = opaque;
CPUState *env = reset_info->env; CPUState *env = reset_info->env;
cpu_reset(env); cpu_state_reset(env);
/* init defaults */ /* init defaults */
env->pc = (uint32_t)reset_info->bootstrap_pc; env->pc = (uint32_t)reset_info->bootstrap_pc;

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@ -45,7 +45,7 @@ static void main_cpu_reset(void *opaque)
{ {
CPUState *env = opaque; CPUState *env = opaque;
cpu_reset(env); cpu_state_reset(env);
env->regs[5] = boot_info.cmdline; env->regs[5] = boot_info.cmdline;
env->regs[7] = boot_info.fdt; env->regs[7] = boot_info.fdt;
env->sregs[SR_PC] = boot_info.bootstrap_pc; env->sregs[SR_PC] = boot_info.bootstrap_pc;

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@ -61,7 +61,7 @@ static void main_cpu_reset(void *opaque)
ResetInfo *reset_info = opaque; ResetInfo *reset_info = opaque;
CPUState *env = reset_info->env; CPUState *env = reset_info->env;
cpu_reset(env); cpu_state_reset(env);
/* init defaults */ /* init defaults */
env->pc = reset_info->bootstrap_pc; env->pc = reset_info->bootstrap_pc;

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@ -200,7 +200,7 @@ static void main_cpu_reset(void *opaque)
{ {
CPUState *env = opaque; CPUState *env = opaque;
cpu_reset(env); cpu_state_reset(env);
/* TODO: 2E reset stuff */ /* TODO: 2E reset stuff */
if (loaderparams.kernel_filename) { if (loaderparams.kernel_filename) {
env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL)); env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));

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@ -51,7 +51,7 @@ enum jazz_model_e
static void main_cpu_reset(void *opaque) static void main_cpu_reset(void *opaque)
{ {
CPUState *env = opaque; CPUState *env = opaque;
cpu_reset(env); cpu_state_reset(env);
} }
static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size) static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size)

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@ -745,7 +745,7 @@ static void malta_mips_config(CPUState *env)
static void main_cpu_reset(void *opaque) static void main_cpu_reset(void *opaque)
{ {
CPUState *env = opaque; CPUState *env = opaque;
cpu_reset(env); cpu_state_reset(env);
/* The bootloader does not need to be rewritten as it is located in a /* The bootloader does not need to be rewritten as it is located in a
read only location. The kernel location and the arguments table read only location. The kernel location and the arguments table

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@ -107,7 +107,7 @@ static void main_cpu_reset(void *opaque)
ResetData *s = (ResetData *)opaque; ResetData *s = (ResetData *)opaque;
CPUState *env = s->env; CPUState *env = s->env;
cpu_reset(env); cpu_state_reset(env);
env->active_tc.PC = s->vector & ~(target_ulong)1; env->active_tc.PC = s->vector & ~(target_ulong)1;
if (s->vector & 1) { if (s->vector & 1) {
env->hflags |= MIPS_HFLAG_M16; env->hflags |= MIPS_HFLAG_M16;

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@ -145,7 +145,7 @@ static void main_cpu_reset(void *opaque)
ResetData *s = (ResetData *)opaque; ResetData *s = (ResetData *)opaque;
CPUState *env = s->env; CPUState *env = s->env;
cpu_reset(env); cpu_state_reset(env);
env->active_tc.PC = s->vector; env->active_tc.PC = s->vector;
} }

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@ -3702,7 +3702,7 @@ static void omap1_mpu_reset(void *opaque)
omap_lpg_reset(mpu->led[0]); omap_lpg_reset(mpu->led[0]);
omap_lpg_reset(mpu->led[1]); omap_lpg_reset(mpu->led[1]);
omap_clkm_reset(mpu); omap_clkm_reset(mpu);
cpu_reset(mpu->env); cpu_state_reset(mpu->env);
} }
static const struct omap_map_s { static const struct omap_map_s {

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@ -2224,7 +2224,7 @@ static void omap2_mpu_reset(void *opaque)
omap_mcspi_reset(mpu->mcspi[1]); omap_mcspi_reset(mpu->mcspi[1]);
omap_i2c_reset(mpu->i2c[0]); omap_i2c_reset(mpu->i2c[0]);
omap_i2c_reset(mpu->i2c[1]); omap_i2c_reset(mpu->i2c[1]);
cpu_reset(mpu->env); cpu_state_reset(mpu->env);
} }
static int omap2_validate_addr(struct omap_mpu_state_s *s, static int omap2_validate_addr(struct omap_mpu_state_s *s,

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@ -928,7 +928,7 @@ static void pc_cpu_reset(void *opaque)
{ {
CPUState *env = opaque; CPUState *env = opaque;
cpu_reset(env); cpu_state_reset(env);
env->halted = !cpu_is_bsp(env); env->halted = !cpu_is_bsp(env);
} }

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@ -147,7 +147,7 @@ static void main_cpu_reset(void *opaque)
{ {
CPUState *env = opaque; CPUState *env = opaque;
cpu_reset(env); cpu_state_reset(env);
env->gpr[1] = (16<<20) - 8; env->gpr[1] = (16<<20) - 8;
env->gpr[3] = FDT_ADDR; env->gpr[3] = FDT_ADDR;
env->nip = entry; env->nip = entry;

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@ -38,6 +38,13 @@
# define LOG_UIC(...) do { } while (0) # define LOG_UIC(...) do { } while (0)
#endif #endif
static void ppc4xx_reset(void *opaque)
{
CPUState *env = opaque;
cpu_state_reset(env);
}
/*****************************************************************************/ /*****************************************************************************/
/* Generic PowerPC 4xx processor instantiation */ /* Generic PowerPC 4xx processor instantiation */
CPUState *ppc4xx_init (const char *cpu_model, CPUState *ppc4xx_init (const char *cpu_model,
@ -60,7 +67,7 @@ CPUState *ppc4xx_init (const char *cpu_model,
tb_clk->opaque = env; tb_clk->opaque = env;
ppc_dcr_init(env, NULL, NULL); ppc_dcr_init(env, NULL, NULL);
/* Register qemu callbacks */ /* Register qemu callbacks */
qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); qemu_register_reset(ppc4xx_reset, env);
return env; return env;
} }

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@ -121,6 +121,13 @@ static target_phys_addr_t round_page(target_phys_addr_t addr)
return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
} }
static void ppc_core99_reset(void *opaque)
{
CPUState *env = opaque;
cpu_state_reset(env);
}
/* PowerPC Mac99 hardware initialisation */ /* PowerPC Mac99 hardware initialisation */
static void ppc_core99_init (ram_addr_t ram_size, static void ppc_core99_init (ram_addr_t ram_size,
const char *boot_device, const char *boot_device,
@ -166,7 +173,7 @@ static void ppc_core99_init (ram_addr_t ram_size,
} }
/* Set time-base frequency to 100 Mhz */ /* Set time-base frequency to 100 Mhz */
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); qemu_register_reset(ppc_core99_reset, env);
} }
/* allocate RAM */ /* allocate RAM */

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@ -65,6 +65,13 @@ static target_phys_addr_t round_page(target_phys_addr_t addr)
return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
} }
static void ppc_heathrow_reset(void *opaque)
{
CPUState *env = opaque;
cpu_state_reset(env);
}
static void ppc_heathrow_init (ram_addr_t ram_size, static void ppc_heathrow_init (ram_addr_t ram_size,
const char *boot_device, const char *boot_device,
const char *kernel_filename, const char *kernel_filename,
@ -104,7 +111,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
} }
/* Set time-base frequency to 16.6 Mhz */ /* Set time-base frequency to 16.6 Mhz */
cpu_ppc_tb_init(env, 16600000UL); cpu_ppc_tb_init(env, 16600000UL);
qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); qemu_register_reset(ppc_heathrow_reset, env);
} }
/* allocate RAM */ /* allocate RAM */

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@ -470,6 +470,13 @@ static void cpu_request_exit(void *opaque, int irq, int level)
} }
} }
static void ppc_prep_reset(void *opaque)
{
CPUState *env = opaque;
cpu_state_reset(env);
}
/* PowerPC PREP hardware initialisation */ /* PowerPC PREP hardware initialisation */
static void ppc_prep_init (ram_addr_t ram_size, static void ppc_prep_init (ram_addr_t ram_size,
const char *boot_device, const char *boot_device,
@ -524,7 +531,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
/* Set time-base frequency to 100 Mhz */ /* Set time-base frequency to 100 Mhz */
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
} }
qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); qemu_register_reset(ppc_prep_reset, env);
} }
/* allocate RAM */ /* allocate RAM */

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@ -198,7 +198,7 @@ static void mpc8544ds_cpu_reset_sec(void *opaque)
{ {
CPUState *env = opaque; CPUState *env = opaque;
cpu_reset(env); cpu_state_reset(env);
/* Secondary CPU starts in halted state for now. Needs to change when /* Secondary CPU starts in halted state for now. Needs to change when
implementing non-kernel boot. */ implementing non-kernel boot. */
@ -211,7 +211,7 @@ static void mpc8544ds_cpu_reset(void *opaque)
CPUState *env = opaque; CPUState *env = opaque;
struct boot_info *bi = env->load_info; struct boot_info *bi = env->load_info;
cpu_reset(env); cpu_state_reset(env);
/* Set initial guest state. */ /* Set initial guest state. */
env->halted = 0; env->halted = 0;

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@ -2045,7 +2045,7 @@ static void pxa2xx_reset(void *opaque, int line, int level)
PXA2xxState *s = (PXA2xxState *) opaque; PXA2xxState *s = (PXA2xxState *) opaque;
if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */ if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
cpu_reset(s->env); cpu_state_reset(s->env);
/* TODO: reset peripherals */ /* TODO: reset peripherals */
} }
} }

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@ -201,7 +201,7 @@ static void main_cpu_reset(void *opaque)
ResetData *s = (ResetData *)opaque; ResetData *s = (ResetData *)opaque;
CPUState *env = s->env; CPUState *env = s->env;
cpu_reset(env); cpu_state_reset(env);
env->pc = s->vector; env->pc = s->vector;
} }

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@ -502,6 +502,13 @@ static void spapr_reset(void *opaque)
} }
static void spapr_cpu_reset(void *opaque)
{
CPUState *env = opaque;
cpu_state_reset(env);
}
/* pSeries LPAR / sPAPR hardware init */ /* pSeries LPAR / sPAPR hardware init */
static void ppc_spapr_init(ram_addr_t ram_size, static void ppc_spapr_init(ram_addr_t ram_size,
const char *boot_device, const char *boot_device,
@ -560,7 +567,7 @@ static void ppc_spapr_init(ram_addr_t ram_size,
} }
/* Set time-base frequency to 512 MHz */ /* Set time-base frequency to 512 MHz */
cpu_ppc_tb_init(env, TIMEBASE_FREQ); cpu_ppc_tb_init(env, TIMEBASE_FREQ);
qemu_register_reset((QEMUResetHandler *)&cpu_reset, env); qemu_register_reset(spapr_cpu_reset, env);
env->hreset_vector = 0x60; env->hreset_vector = 0x60;
env->hreset_excp_prefix = 0; env->hreset_excp_prefix = 0;

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@ -283,7 +283,7 @@ static void main_cpu_reset(void *opaque)
{ {
CPUState *env = opaque; CPUState *env = opaque;
cpu_reset(env); cpu_state_reset(env);
env->halted = 0; env->halted = 0;
} }
@ -291,7 +291,7 @@ static void secondary_cpu_reset(void *opaque)
{ {
CPUState *env = opaque; CPUState *env = opaque;
cpu_reset(env); cpu_state_reset(env);
env->halted = 1; env->halted = 1;
} }

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@ -376,7 +376,7 @@ static void main_cpu_reset(void *opaque)
CPUState *env = s->env; CPUState *env = s->env;
static unsigned int nr_resets; static unsigned int nr_resets;
cpu_reset(env); cpu_state_reset(env);
cpu_timer_reset(env->tick); cpu_timer_reset(env->tick);
cpu_timer_reset(env->stick); cpu_timer_reset(env->stick);

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@ -109,7 +109,7 @@ static void main_cpu_reset(void *opaque)
CPUState *env = opaque; CPUState *env = opaque;
struct boot_info *bi = env->load_info; struct boot_info *bi = env->load_info;
cpu_reset(env); cpu_state_reset(env);
/* Linux Kernel Parameters (passing device tree): /* Linux Kernel Parameters (passing device tree):
* r3: pointer to the fdt * r3: pointer to the fdt
* r4: 0 * r4: 0

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@ -146,9 +146,11 @@ static uint64_t translate_phys_addr(void *env, uint64_t addr)
return cpu_get_phys_page_debug(env, addr); return cpu_get_phys_page_debug(env, addr);
} }
static void lx60_reset(void *env) static void lx60_reset(void *opaque)
{ {
cpu_reset(env); CPUState *env = opaque;
cpu_state_reset(env);
} }
static void lx_init(const LxBoardDesc *board, static void lx_init(const LxBoardDesc *board,
@ -183,7 +185,7 @@ static void lx_init(const LxBoardDesc *board,
/* Need MMU initialized prior to ELF loading, /* Need MMU initialized prior to ELF loading,
* so that ELF gets loaded into virtual addresses * so that ELF gets loaded into virtual addresses
*/ */
cpu_reset(env); cpu_state_reset(env);
} }
ram = g_malloc(sizeof(*ram)); ram = g_malloc(sizeof(*ram));

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@ -39,7 +39,7 @@ static uint64_t translate_phys_addr(void *env, uint64_t addr)
static void sim_reset(void *env) static void sim_reset(void *env)
{ {
cpu_reset(env); cpu_state_reset(env);
} }
static void sim_init(ram_addr_t ram_size, static void sim_init(ram_addr_t ram_size,

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@ -3375,7 +3375,7 @@ int main(int argc, char **argv, char **envp)
exit(1); exit(1);
} }
#if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC) #if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC)
cpu_reset(env); cpu_state_reset(env);
#endif #endif
thread_env = env; thread_env = env;

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@ -4036,7 +4036,7 @@ static int do_fork(CPUState *env, unsigned int flags, abi_ulong newsp,
/* we create a new CPU instance. */ /* we create a new CPU instance. */
new_env = cpu_copy(env); new_env = cpu_copy(env);
#if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC) #if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC)
cpu_reset(new_env); cpu_state_reset(new_env);
#endif #endif
/* Init regs that differ from the parent. */ /* Init regs that differ from the parent. */
cpu_clone_regs(new_env, newsp); cpu_clone_regs(new_env, newsp);

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@ -278,7 +278,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
} }
} }
void cpu_reset(CPUARMState *env) void cpu_state_reset(CPUARMState *env)
{ {
uint32_t id; uint32_t id;
uint32_t tmp = 0; uint32_t tmp = 0;
@ -416,7 +416,7 @@ CPUARMState *cpu_arm_init(const char *cpu_model)
env->cpu_model_str = cpu_model; env->cpu_model_str = cpu_model;
env->cp15.c0_cpuid = id; env->cp15.c0_cpuid = id;
cpu_reset(env); cpu_state_reset(env);
if (arm_feature(env, ARM_FEATURE_NEON)) { if (arm_feature(env, ARM_FEATURE_NEON)) {
gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
51, "arm-neon.xml", 0); 51, "arm-neon.xml", 0);

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@ -3513,7 +3513,7 @@ CPUCRISState *cpu_cris_init (const char *cpu_model)
env->pregs[PR_VR] = vr_by_name(cpu_model); env->pregs[PR_VR] = vr_by_name(cpu_model);
cpu_exec_init(env); cpu_exec_init(env);
cpu_reset(env); cpu_state_reset(env);
qemu_init_vcpu(env); qemu_init_vcpu(env);
if (tcg_initialized) if (tcg_initialized)
@ -3573,7 +3573,7 @@ CPUCRISState *cpu_cris_init (const char *cpu_model)
return env; return env;
} }
void cpu_reset (CPUCRISState *env) void cpu_state_reset(CPUCRISState *env)
{ {
uint32_t vr; uint32_t vr;

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@ -27,7 +27,7 @@
//#define DEBUG_MMU //#define DEBUG_MMU
/* NOTE: must be called outside the CPU execute loop */ /* NOTE: must be called outside the CPU execute loop */
void cpu_reset(CPUX86State *env) void cpu_state_reset(CPUState *env)
{ {
int i; int i;
@ -1282,7 +1282,7 @@ void do_cpu_init(CPUState *env)
int sipi = env->interrupt_request & CPU_INTERRUPT_SIPI; int sipi = env->interrupt_request & CPU_INTERRUPT_SIPI;
uint64_t pat = env->pat; uint64_t pat = env->pat;
cpu_reset(env); cpu_state_reset(env);
env->interrupt_request = sipi; env->interrupt_request = sipi;
env->pat = pat; env->pat = pat;
apic_init_reset(env->apic_state); apic_init_reset(env->apic_state);

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@ -212,7 +212,7 @@ CPUState *cpu_lm32_init(const char *cpu_model)
env->flags = 0; env->flags = 0;
cpu_exec_init(env); cpu_exec_init(env);
cpu_reset(env); cpu_state_reset(env);
qemu_init_vcpu(env); qemu_init_vcpu(env);
if (!tcg_initialized) { if (!tcg_initialized) {
@ -235,7 +235,7 @@ void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value)
} }
} }
void cpu_reset(CPUState *env) void cpu_state_reset(CPUState *env)
{ {
if (qemu_loglevel_mask(CPU_LOG_RESET)) { if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);

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@ -143,7 +143,7 @@ static int cpu_m68k_set_model(CPUM68KState *env, const char *name)
return 0; return 0;
} }
void cpu_reset(CPUM68KState *env) void cpu_state_reset(CPUM68KState *env)
{ {
if (qemu_loglevel_mask(CPU_LOG_RESET)) { if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
@ -181,7 +181,7 @@ CPUM68KState *cpu_m68k_init(const char *cpu_model)
return NULL; return NULL;
} }
cpu_reset(env); cpu_state_reset(env);
qemu_init_vcpu(env); qemu_init_vcpu(env);
return env; return env;
} }

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@ -1897,7 +1897,7 @@ CPUState *cpu_mb_init (const char *cpu_model)
env = g_malloc0(sizeof(CPUState)); env = g_malloc0(sizeof(CPUState));
cpu_exec_init(env); cpu_exec_init(env);
cpu_reset(env); cpu_state_reset(env);
qemu_init_vcpu(env); qemu_init_vcpu(env);
set_float_rounding_mode(float_round_nearest_even, &env->fp_status); set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
@ -1939,7 +1939,7 @@ CPUState *cpu_mb_init (const char *cpu_model)
return env; return env;
} }
void cpu_reset (CPUState *env) void cpu_state_reset(CPUState *env)
{ {
if (qemu_loglevel_mask(CPU_LOG_RESET)) { if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);

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@ -452,7 +452,7 @@ void do_interrupt (CPUState *env)
set_hflags_for_handler(env); set_hflags_for_handler(env);
break; break;
case EXCP_RESET: case EXCP_RESET:
cpu_reset(env); cpu_state_reset(env);
break; break;
case EXCP_SRESET: case EXCP_SRESET:
env->CP0_Status |= (1 << CP0St_SR); env->CP0_Status |= (1 << CP0St_SR);

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@ -12708,12 +12708,12 @@ CPUMIPSState *cpu_mips_init (const char *cpu_model)
fpu_init(env, def); fpu_init(env, def);
mvp_init(env, def); mvp_init(env, def);
mips_tcg_init(); mips_tcg_init();
cpu_reset(env); cpu_state_reset(env);
qemu_init_vcpu(env); qemu_init_vcpu(env);
return env; return env;
} }
void cpu_reset (CPUMIPSState *env) void cpu_state_reset(CPUMIPSState *env)
{ {
if (qemu_loglevel_mask(CPU_LOG_RESET)) { if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);

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@ -3136,7 +3136,7 @@ void cpu_dump_rfi (target_ulong RA, target_ulong msr)
TARGET_FMT_lx "\n", RA, msr); TARGET_FMT_lx "\n", RA, msr);
} }
void cpu_reset(CPUPPCState *env) void cpu_state_reset(CPUPPCState *env)
{ {
target_ulong msr; target_ulong msr;

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@ -95,7 +95,7 @@ CPUS390XState *cpu_s390x_init(const char *cpu_model)
env->cpu_model_str = cpu_model; env->cpu_model_str = cpu_model;
env->cpu_num = cpu_num++; env->cpu_num = cpu_num++;
env->ext_index = -1; env->ext_index = -1;
cpu_reset(env); cpu_state_reset(env);
qemu_init_vcpu(env); qemu_init_vcpu(env);
return env; return env;
} }
@ -119,7 +119,7 @@ int cpu_s390x_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
#endif /* CONFIG_USER_ONLY */ #endif /* CONFIG_USER_ONLY */
void cpu_reset(CPUS390XState *env) void cpu_state_reset(CPUS390XState *env)
{ {
if (qemu_loglevel_mask(CPU_LOG_RESET)) { if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);

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@ -178,7 +178,7 @@ void cpu_dump_state(CPUState * env, FILE * f,
} }
} }
void cpu_reset(CPUSH4State * env) void cpu_state_reset(CPUSH4State *env)
{ {
if (qemu_loglevel_mask(CPU_LOG_RESET)) { if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
@ -279,7 +279,7 @@ CPUSH4State *cpu_sh4_init(const char *cpu_model)
env->movcal_backup_tail = &(env->movcal_backup); env->movcal_backup_tail = &(env->movcal_backup);
sh4_translate_init(); sh4_translate_init();
env->cpu_model_str = cpu_model; env->cpu_model_str = cpu_model;
cpu_reset(env); cpu_state_reset(env);
cpu_register(env, def); cpu_register(env, def);
qemu_init_vcpu(env); qemu_init_vcpu(env);
return env; return env;

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@ -23,7 +23,7 @@
static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model); static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model);
void cpu_reset(CPUSPARCState *env) void cpu_state_reset(CPUSPARCState *env)
{ {
if (qemu_loglevel_mask(CPU_LOG_RESET)) { if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);

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@ -35,7 +35,7 @@
static void reset_mmu(CPUState *env); static void reset_mmu(CPUState *env);
void cpu_reset(CPUXtensaState *env) void cpu_state_reset(CPUXtensaState *env)
{ {
env->exception_taken = 0; env->exception_taken = 0;
env->pc = env->config->exception_vector[EXC_RESET]; env->pc = env->config->exception_vector[EXC_RESET];