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target-arm: convert disas_neon_ls_insn not to use cpu_T 

Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Filip Navara 2009-10-15 13:07:21 +02:00 committed by Aurelien Jarno
parent dd8fbd787e
commit 1b2b1e547b
1 changed files with 34 additions and 33 deletions
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67
target-arm/translate.c
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@ -3764,6 +3764,7 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
int load; int load;
int shift; int shift;
int n; int n;
TCGv addr;
TCGv tmp; TCGv tmp;
TCGv tmp2; TCGv tmp2;
@ -3773,6 +3774,7 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
rn = (insn >> 16) & 0xf; rn = (insn >> 16) & 0xf;
rm = insn & 0xf; rm = insn & 0xf;
load = (insn & (1 << 21)) != 0; load = (insn & (1 << 21)) != 0;
addr = new_tmp();
if ((insn & (1 << 23)) == 0) { if ((insn & (1 << 23)) == 0) {
/* Load store all elements. */ /* Load store all elements. */
op = (insn >> 8) & 0xf; op = (insn >> 8) & 0xf;
@ -3781,32 +3783,30 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
return 1; return 1;
nregs = neon_ls_element_type[op].nregs; nregs = neon_ls_element_type[op].nregs;
interleave = neon_ls_element_type[op].interleave; interleave = neon_ls_element_type[op].interleave;
gen_movl_T1_reg(s, rn); tcg_gen_mov_i32(addr, cpu_R[rn]);
stride = (1 << size) * interleave; stride = (1 << size) * interleave;
for (reg = 0; reg < nregs; reg++) { for (reg = 0; reg < nregs; reg++) {
if (interleave > 2 || (interleave == 2 && nregs == 2)) { if (interleave > 2 || (interleave == 2 && nregs == 2)) {
gen_movl_T1_reg(s, rn); tcg_gen_addi_i32(addr, cpu_R[rn], (1 << size) * reg);
gen_op_addl_T1_im((1 << size) * reg);
} else if (interleave == 2 && nregs == 4 && reg == 2) { } else if (interleave == 2 && nregs == 4 && reg == 2) {
gen_movl_T1_reg(s, rn); tcg_gen_addi_i32(addr, cpu_R[rn], 1 << size);
gen_op_addl_T1_im(1 << size);
} }
for (pass = 0; pass < 2; pass++) { for (pass = 0; pass < 2; pass++) {
if (size == 2) { if (size == 2) {
if (load) { if (load) {
tmp = gen_ld32(cpu_T[1], IS_USER(s)); tmp = gen_ld32(addr, IS_USER(s));
neon_store_reg(rd, pass, tmp); neon_store_reg(rd, pass, tmp);
} else { } else {
tmp = neon_load_reg(rd, pass); tmp = neon_load_reg(rd, pass);
gen_st32(tmp, cpu_T[1], IS_USER(s)); gen_st32(tmp, addr, IS_USER(s));
} }
gen_op_addl_T1_im(stride); tcg_gen_addi_i32(addr, addr, stride);
} else if (size == 1) { } else if (size == 1) {
if (load) { if (load) {
tmp = gen_ld16u(cpu_T[1], IS_USER(s)); tmp = gen_ld16u(addr, IS_USER(s));
gen_op_addl_T1_im(stride); tcg_gen_addi_i32(addr, addr, stride);
tmp2 = gen_ld16u(cpu_T[1], IS_USER(s)); tmp2 = gen_ld16u(addr, IS_USER(s));
gen_op_addl_T1_im(stride); tcg_gen_addi_i32(addr, addr, stride);
gen_bfi(tmp, tmp, tmp2, 16, 0xffff); gen_bfi(tmp, tmp, tmp2, 16, 0xffff);
dead_tmp(tmp2); dead_tmp(tmp2);
neon_store_reg(rd, pass, tmp); neon_store_reg(rd, pass, tmp);
@ -3814,17 +3814,17 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
tmp = neon_load_reg(rd, pass); tmp = neon_load_reg(rd, pass);
tmp2 = new_tmp(); tmp2 = new_tmp();
tcg_gen_shri_i32(tmp2, tmp, 16); tcg_gen_shri_i32(tmp2, tmp, 16);
gen_st16(tmp, cpu_T[1], IS_USER(s)); gen_st16(tmp, addr, IS_USER(s));
gen_op_addl_T1_im(stride); tcg_gen_addi_i32(addr, addr, stride);
gen_st16(tmp2, cpu_T[1], IS_USER(s)); gen_st16(tmp2, addr, IS_USER(s));
gen_op_addl_T1_im(stride); tcg_gen_addi_i32(addr, addr, stride);
} }
} else /* size == 0 */ { } else /* size == 0 */ {
if (load) { if (load) {
TCGV_UNUSED(tmp2); TCGV_UNUSED(tmp2);
for (n = 0; n < 4; n++) { for (n = 0; n < 4; n++) {
tmp = gen_ld8u(cpu_T[1], IS_USER(s)); tmp = gen_ld8u(addr, IS_USER(s));
gen_op_addl_T1_im(stride); tcg_gen_addi_i32(addr, addr, stride);
if (n == 0) { if (n == 0) {
tmp2 = tmp; tmp2 = tmp;
} else { } else {
@ -3842,8 +3842,8 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
} else { } else {
tcg_gen_shri_i32(tmp, tmp2, n * 8); tcg_gen_shri_i32(tmp, tmp2, n * 8);
} }
gen_st8(tmp, cpu_T[1], IS_USER(s)); gen_st8(tmp, addr, IS_USER(s));
gen_op_addl_T1_im(stride); tcg_gen_addi_i32(addr, addr, stride);
} }
dead_tmp(tmp2); dead_tmp(tmp2);
} }
@ -3861,26 +3861,26 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
size = (insn >> 6) & 3; size = (insn >> 6) & 3;
nregs = ((insn >> 8) & 3) + 1; nregs = ((insn >> 8) & 3) + 1;
stride = (insn & (1 << 5)) ? 2 : 1; stride = (insn & (1 << 5)) ? 2 : 1;
gen_movl_T1_reg(s, rn); tcg_gen_mov_i32(addr, cpu_R[rn]);
for (reg = 0; reg < nregs; reg++) { for (reg = 0; reg < nregs; reg++) {
switch (size) { switch (size) {
case 0: case 0:
tmp = gen_ld8u(cpu_T[1], IS_USER(s)); tmp = gen_ld8u(addr, IS_USER(s));
gen_neon_dup_u8(tmp, 0); gen_neon_dup_u8(tmp, 0);
break; break;
case 1: case 1:
tmp = gen_ld16u(cpu_T[1], IS_USER(s)); tmp = gen_ld16u(addr, IS_USER(s));
gen_neon_dup_low16(tmp); gen_neon_dup_low16(tmp);
break; break;
case 2: case 2:
tmp = gen_ld32(cpu_T[0], IS_USER(s)); tmp = gen_ld32(addr, IS_USER(s));
break; break;
case 3: case 3:
return 1; return 1;
default: /* Avoid compiler warnings. */ default: /* Avoid compiler warnings. */
abort(); abort();
} }
gen_op_addl_T1_im(1 << size); tcg_gen_addi_i32(addr, addr, 1 << size);
tmp2 = new_tmp(); tmp2 = new_tmp();
tcg_gen_mov_i32(tmp2, tmp); tcg_gen_mov_i32(tmp2, tmp);
neon_store_reg(rd, 0, tmp2); neon_store_reg(rd, 0, tmp2);
@ -3908,18 +3908,18 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
abort(); abort();
} }
nregs = ((insn >> 8) & 3) + 1; nregs = ((insn >> 8) & 3) + 1;
gen_movl_T1_reg(s, rn); tcg_gen_mov_i32(addr, cpu_R[rn]);
for (reg = 0; reg < nregs; reg++) { for (reg = 0; reg < nregs; reg++) {
if (load) { if (load) {
switch (size) { switch (size) {
case 0: case 0:
tmp = gen_ld8u(cpu_T[1], IS_USER(s)); tmp = gen_ld8u(addr, IS_USER(s));
break; break;
case 1: case 1:
tmp = gen_ld16u(cpu_T[1], IS_USER(s)); tmp = gen_ld16u(addr, IS_USER(s));
break; break;
case 2: case 2:
tmp = gen_ld32(cpu_T[1], IS_USER(s)); tmp = gen_ld32(addr, IS_USER(s));
break; break;
default: /* Avoid compiler warnings. */ default: /* Avoid compiler warnings. */
abort(); abort();
@ -3936,22 +3936,23 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
tcg_gen_shri_i32(tmp, tmp, shift); tcg_gen_shri_i32(tmp, tmp, shift);
switch (size) { switch (size) {
case 0: case 0:
gen_st8(tmp, cpu_T[1], IS_USER(s)); gen_st8(tmp, addr, IS_USER(s));
break; break;
case 1: case 1:
gen_st16(tmp, cpu_T[1], IS_USER(s)); gen_st16(tmp, addr, IS_USER(s));
break; break;
case 2: case 2:
gen_st32(tmp, cpu_T[1], IS_USER(s)); gen_st32(tmp, addr, IS_USER(s));
break; break;
} }
} }
rd += stride; rd += stride;
gen_op_addl_T1_im(1 << size); tcg_gen_addi_i32(addr, addr, 1 << size);
} }
stride = nregs * (1 << size); stride = nregs * (1 << size);
} }
} }
dead_tmp(addr);
if (rm != 15) { if (rm != 15) {
TCGv base; TCGv base;