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target-xtensa: implement S32NB 

S32NB provides the same functionality as S32I with two exceptions.
First, when its operation leaves the processor, the external transaction
is marked Non-Bufferable. Second, it may not be used to write to
Instruction RAM.
In QEMU S32NB is equivalent to S32I.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2015-07-19 09:49:00 +03:00
parent 5eeb40c5b1
commit 19b7bec4a3
1 changed files with 11 additions and 0 deletions
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11
target-xtensa/translate.c
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@ -1965,6 +1965,17 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
}
break;
case 5: /*S32N*/
if (gen_window_check2(dc, RRI4_S, RRI4_T)) {
TCGv_i32 addr = tcg_temp_new_i32();
tcg_gen_addi_i32(addr, cpu_R[RRI4_S], RRI4_IMM4 << 2);
gen_load_store_alignment(dc, 2, addr, false);
tcg_gen_qemu_st32(cpu_R[RRI4_T], addr, dc->cring);
tcg_temp_free(addr);
}
break;
default:
RESERVED();
break;