From 19a18edd8860064d3dbe71bc5315347bcfeb4c24 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Wed, 21 Jun 2023 16:23:01 +0200 Subject: [PATCH] target/tricore: Honour privilege changes on PSW write the CPU can change the privilege level by writing the corresponding bits in PSW. If this happens all instructions after this 'mtcr' in the TB are translated with the wrong privilege level. So we have to exit to the cpu_loop() and start translating again with the new privilege level. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Message-Id: <20230621142302.1648383-8-kbastian@mail.uni-paderborn.de> --- target/tricore/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 82b61e912e..9e408f44ec 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -334,7 +334,6 @@ static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea) tcg_gen_mov_tl(cpu_gpr_d[reg], temp); } - /* We generate loads and store to core special function register (csfr) through the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3 makros R, A and E, which allow read-only, all and endinit protected access. @@ -382,6 +381,7 @@ static inline void gen_mtcr(DisasContext *ctx, TCGv r1, /* since we're caching PSW make this a special case */ if (offset == 0xfe04) { gen_helper_psw_write(cpu_env, r1); + ctx->base.is_jmp = DISAS_EXIT_UPDATE; } else { switch (offset) { #include "csfr.h.inc"