mirror of https://github.com/xemu-project/xemu.git
target/arm: Correct load exclusive pair atomicity
We are not providing the required single-copy atomic semantics for the 64-bit operation that is the 32-bit paired load. At the same time, leave the entire 64-bit value in cpu_exclusive_val and stop writing to cpu_exclusive_high. This means that we do not have to re-assemble the 64-bit quantity when it comes time to store. At the same time, drop a redundant temporary and perform all loads directly into the cpu_exclusive_* globals. Tested-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20170815145714.17635-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -1853,29 +1853,42 @@ static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
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static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
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TCGv_i64 addr, int size, bool is_pair)
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{
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TCGv_i64 tmp = tcg_temp_new_i64();
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TCGMemOp memop = s->be_data + size;
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int idx = get_mem_index(s);
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TCGMemOp memop = s->be_data;
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g_assert(size <= 3);
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tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), memop);
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if (is_pair) {
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TCGv_i64 addr2 = tcg_temp_new_i64();
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TCGv_i64 hitmp = tcg_temp_new_i64();
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g_assert(size >= 2);
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tcg_gen_addi_i64(addr2, addr, 1 << size);
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tcg_gen_qemu_ld_i64(hitmp, addr2, get_mem_index(s), memop);
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tcg_temp_free_i64(addr2);
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tcg_gen_mov_i64(cpu_exclusive_high, hitmp);
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tcg_gen_mov_i64(cpu_reg(s, rt2), hitmp);
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tcg_temp_free_i64(hitmp);
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if (size == 2) {
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/* The pair must be single-copy atomic for the doubleword. */
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memop |= MO_64;
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tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop);
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if (s->be_data == MO_LE) {
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tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 0, 32);
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tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 32, 32);
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} else {
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tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 32, 32);
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tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 0, 32);
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}
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} else {
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/* The pair must be single-copy atomic for *each* doubleword,
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but not the entire quadword. */
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memop |= MO_64;
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tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop);
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TCGv_i64 addr2 = tcg_temp_new_i64();
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tcg_gen_addi_i64(addr2, addr, 8);
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tcg_gen_qemu_ld_i64(cpu_exclusive_high, addr2, idx, memop);
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tcg_temp_free_i64(addr2);
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tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val);
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tcg_gen_mov_i64(cpu_reg(s, rt2), cpu_exclusive_high);
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}
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} else {
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memop |= size;
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tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop);
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tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val);
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}
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tcg_gen_mov_i64(cpu_exclusive_val, tmp);
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tcg_gen_mov_i64(cpu_reg(s, rt), tmp);
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tcg_temp_free_i64(tmp);
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tcg_gen_mov_i64(cpu_exclusive_addr, addr);
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}
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@ -1908,14 +1921,15 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
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tmp = tcg_temp_new_i64();
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if (is_pair) {
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if (size == 2) {
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TCGv_i64 val = tcg_temp_new_i64();
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tcg_gen_concat32_i64(tmp, cpu_reg(s, rt), cpu_reg(s, rt2));
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tcg_gen_concat32_i64(val, cpu_exclusive_val, cpu_exclusive_high);
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tcg_gen_atomic_cmpxchg_i64(tmp, addr, val, tmp,
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if (s->be_data == MO_LE) {
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tcg_gen_concat32_i64(tmp, cpu_reg(s, rt), cpu_reg(s, rt2));
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} else {
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tcg_gen_concat32_i64(tmp, cpu_reg(s, rt2), cpu_reg(s, rt));
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}
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tcg_gen_atomic_cmpxchg_i64(tmp, addr, cpu_exclusive_val, tmp,
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get_mem_index(s),
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MO_64 | MO_ALIGN | s->be_data);
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tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, val);
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tcg_temp_free_i64(val);
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tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val);
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} else if (s->be_data == MO_LE) {
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gen_helper_paired_cmpxchg64_le(tmp, cpu_env, addr, cpu_reg(s, rt),
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cpu_reg(s, rt2));
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