From c92023bfd18c968d615b715522467f7354db5877 Mon Sep 17 00:00:00 2001 From: Aleksandar Markovic Date: Mon, 18 Jun 2018 20:29:40 +0200 Subject: [PATCH 1/9] MAINTAINERS: update target-mips maintainers Yongbok Kim transfers duties of QEMU for target MIPS maintainer to myself as he leaves MIPS. Many thanks to Yongbok for his substantial contributing to QEMU for MIPS over many years and taking care of its maintainance for almost two years. Signed-off-by: Aleksandar Markovic Acked-by: Yongbok Kim Reviewed-by: Aleksandar Markovic --- MAINTAINERS | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 8c626f6a07..42a1892d6a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -187,7 +187,7 @@ F: disas/microblaze.c MIPS M: Aurelien Jarno -M: Yongbok Kim +M: Aleksandar Markovic S: Maintained F: target/mips/ F: hw/mips/ @@ -718,7 +718,7 @@ S: Maintained F: hw/mips/mips_malta.c Mipssim -M: Yongbok Kim +M: Aleksandar Markovic S: Odd Fixes F: hw/mips/mips_mipssim.c F: hw/net/mipsnet.c @@ -729,7 +729,7 @@ S: Maintained F: hw/mips/mips_r4k.c Fulong 2E -M: Yongbok Kim +M: Aleksandar Markovic S: Odd Fixes F: hw/mips/mips_fulong2e.c F: hw/isa/vt82c686.c From 9581eeebe3ffd37f7fde270f92c96a2c5ebb860c Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 4 Jun 2018 12:03:57 +0100 Subject: [PATCH 2/9] hw/mips/boston: don't make flash region 'nomigrate' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently we use memory_region_init_rom_nomigrate() to create the "boston.flash" memory region, and we don't manually register it with vmstate_register_ram(). This currently means that its contents are migrated but as a ram block whose name is the empty string; in future it may mean they are not migrated at all. Use memory_region_init_ram() instead. Note that this is a a cross-version migration compatibility break for the "boston" machine. Signed-off-by: Peter Maydell Reviewed-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Paul Burton Signed-off-by: Aleksandar Markovic --- hw/mips/boston.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 52cce19766..14e6f955d2 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -471,8 +471,7 @@ static void boston_mach_init(MachineState *machine) sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->cps), 0, 0, 1); flash = g_new(MemoryRegion, 1); - memory_region_init_rom_nomigrate(flash, NULL, - "boston.flash", 128 * M_BYTE, &err); + memory_region_init_rom(flash, NULL, "boston.flash", 128 * M_BYTE, &err); memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0); ddr = g_new(MemoryRegion, 1); From 917b77f5e5a713c217ecc962fd8c491aa9b586aa Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 4 Jun 2018 12:03:58 +0100 Subject: [PATCH 3/9] hw/mips/mips_malta: don't make bios region 'nomigrate' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently we use memory_region_init_rom_nomigrate() to create the "bios.1fc" memory region, and we don't manually register it with vmstate_register_ram(). This currently means that its contents are migrated but as a ram block whose name is the empty string; in future it may mean they are not migrated at all. Use memory_region_init_ram() instead. Note that this is a a cross-version migration compatibility break for the "malta" machine. Signed-off-by: Peter Maydell Reviewed-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Paul Burton Signed-off-by: Aleksandar Markovic --- hw/mips/mips_malta.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 494f84e290..b9d92bf47e 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -1152,7 +1152,7 @@ void mips_malta_init(MachineState *machine) * handled by an overlapping region as the resulting ROM code subpage * regions are not executable. */ - memory_region_init_ram_nomigrate(bios_copy, NULL, "bios.1fc", BIOS_SIZE, + memory_region_init_ram(bios_copy, NULL, "bios.1fc", BIOS_SIZE, &error_fatal); if (!rom_copy(memory_region_get_ram_ptr(bios_copy), FLASH_ADDRESS, BIOS_SIZE)) { From 4f91740698ced512fdad8540eb0bd232fc70aadd Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 19 Jun 2018 13:07:30 +0100 Subject: [PATCH 4/9] hw/pci-host/xilinx-pcie: don't make "io" region be RAM Currently we use memory_region_init_rom_nomigrate() to create the "io" memory region to pass to pci_register_root_bus(). This is a dummy region, because this PCI controller doesn't support accesses to PCI IO space. There is no reason for the dummy region to be a RAM region; it is only used as a place where PCI BARs can be mapped, and if you could get a PCI card to do a bus master access to the IO space it should not get acts-like-RAM behaviour. Use a simple container memory region instead. (We do have one PCI card model which can do bus master accesses to IO space -- the LSI53C895A SCSI adaptor.) This avoids the oddity of having a memory region which is RAM but where the RAM is not migrated. Note that the size of the region we use here has no effect on behaviour. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Signed-off-by: Aleksandar Markovic --- hw/pci-host/xilinx-pcie.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/xilinx-pcie.c b/hw/pci-host/xilinx-pcie.c index 044e312dc1..b0a31b917d 100644 --- a/hw/pci-host/xilinx-pcie.c +++ b/hw/pci-host/xilinx-pcie.c @@ -120,9 +120,8 @@ static void xilinx_pcie_host_realize(DeviceState *dev, Error **errp) memory_region_init(&s->mmio, OBJECT(s), "mmio", UINT64_MAX); memory_region_set_enabled(&s->mmio, false); - /* dummy I/O region */ - memory_region_init_ram_nomigrate(&s->io, OBJECT(s), "io", 16, NULL); - memory_region_set_enabled(&s->io, false); + /* dummy PCI I/O region (not visible to the CPU) */ + memory_region_init(&s->io, OBJECT(s), "io", 16); /* interrupt out */ qdev_init_gpio_out_named(dev, &s->irq, "interrupt_out", 1); From f48a2cb21824217a61ec7be797860a0702e5325c Mon Sep 17 00:00:00 2001 From: Yongbok Kim Date: Wed, 20 Jun 2018 13:05:46 +0100 Subject: [PATCH 5/9] target/mips: Raise a RI when given fs is n/a from CTC1 Fix to raise a Reserved Instruction exception when given fs is not available from CTC1. Signed-off-by: Yongbok Kim Reviewed-by: Aleksandar Markovic Signed-off-by: Aleksandar Markovic --- target/mips/op_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 9025f42366..41d3634289 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -2627,6 +2627,9 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt) (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask)); break; default: + if (env->insn_flags & ISA_MIPS32R6) { + do_raise_exception(env, EXCP_RI, GETPC()); + } return; } restore_fp_status(env); From 0305d194be1dbda09fa7a7c883894030d07c355f Mon Sep 17 00:00:00 2001 From: Yongbok Kim Date: Wed, 20 Jun 2018 13:05:47 +0100 Subject: [PATCH 6/9] target/mips: Fix microMIPS on reset Fix to activate microMIPS on reset when Config3.ISA == {1, 3} Signed-off-by: Yongbok Kim Reviewed-by: Aleksandar Markovic Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index e57d71e485..2eb211ae8c 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20713,6 +20713,11 @@ void cpu_state_reset(CPUMIPSState *env) env->CP0_Status |= (1 << CP0St_FR); } + if (env->CP0_Config3 & (1 << CP0C3_ISA)) { + /* microMIPS on reset when Config3.ISA == {1, 3} */ + env->hflags |= MIPS_HFLAG_M16; + } + /* MSA */ if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { msa_reset(env); From b52d3bfa2d54d99ef25f6d008815eecc53b67bfe Mon Sep 17 00:00:00 2001 From: Yongbok Kim Date: Wed, 20 Jun 2018 13:05:58 +0100 Subject: [PATCH 7/9] target/mips: Update gen_flt_ldst() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update gen_flt_ldst() in order to reuse the functions for nanoMIPS Signed-off-by: Yongbok Kim Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 2eb211ae8c..e923d2739b 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2433,11 +2433,8 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt, /* Load and store */ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, - int base, int16_t offset) + TCGv t0) { - TCGv t0 = tcg_temp_new(); - - gen_base_offset_addr(ctx, t0, base, offset); /* Don't do NOP if destination is zero: we must perform the actual memory access. */ switch (opc) { @@ -2480,15 +2477,15 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, default: MIPS_INVAL("flt_ldst"); generate_exception_end(ctx, EXCP_RI); - goto out; + break; } - out: - tcg_temp_free(t0); } static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt, int rs, int16_t imm) { + TCGv t0 = tcg_temp_new(); + if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { check_cp1_enabled(ctx); switch (op) { @@ -2497,11 +2494,13 @@ static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt, check_insn(ctx, ISA_MIPS2); /* Fallthrough */ default: - gen_flt_ldst(ctx, op, rt, rs, imm); + gen_base_offset_addr(ctx, t0, rs, imm); + gen_flt_ldst(ctx, op, rt, t0); } } else { generate_exception_err(ctx, EXCP_CpU, 1); } + tcg_temp_free(t0); } /* Arithmetic with immediate operand */ From 72e1f16f18fe62504f8f25d7a3f6813b24b221be Mon Sep 17 00:00:00 2001 From: Yongbok Kim Date: Wed, 20 Jun 2018 13:06:07 +0100 Subject: [PATCH 8/9] target/mips: Fix data type for offset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Offset can be larger than 16 bit from nanoMIPS, and immediate field can be larger than 16 bits as well. Signed-off-by: Yongbok Kim Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index e923d2739b..20b43c0337 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2112,7 +2112,7 @@ OP_ST_ATOMIC(scd,st64,ld64,0x7); #undef OP_ST_ATOMIC static void gen_base_offset_addr (DisasContext *ctx, TCGv addr, - int base, int16_t offset) + int base, int offset) { if (base == 0) { tcg_gen_movi_tl(addr, offset); @@ -2140,7 +2140,7 @@ static target_ulong pc_relative_pc (DisasContext *ctx) /* Load */ static void gen_ld(DisasContext *ctx, uint32_t opc, - int rt, int base, int16_t offset) + int rt, int base, int offset) { TCGv t0, t1, t2; int mem_idx = ctx->mem_idx; @@ -2337,7 +2337,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, /* Store */ static void gen_st (DisasContext *ctx, uint32_t opc, int rt, - int base, int16_t offset) + int base, int offset) { TCGv t0 = tcg_temp_new(); TCGv t1 = tcg_temp_new(); @@ -2505,7 +2505,7 @@ static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt, /* Arithmetic with immediate operand */ static void gen_arith_imm(DisasContext *ctx, uint32_t opc, - int rt, int rs, int16_t imm) + int rt, int rs, int imm) { target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */ From 8e0b373f8aa4b9feec7b44029455587e2e3d2b0f Mon Sep 17 00:00:00 2001 From: Yongbok Kim Date: Wed, 20 Jun 2018 13:06:18 +0100 Subject: [PATCH 9/9] target/mips: Fix gdbstub to read/write 64 bit FP registers Fix gdbstub to read/write 64 bit FP registers Signed-off-by: Yongbok Kim Reviewed-by: Aleksandar Markovic Signed-off-by: Aleksandar Markovic --- target/mips/gdbstub.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c index 6d1fb70f2c..18e0e6dce4 100644 --- a/target/mips/gdbstub.c +++ b/target/mips/gdbstub.c @@ -39,7 +39,7 @@ int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0); default: if (env->CP0_Status & (1 << CP0St_FR)) { - return gdb_get_regl(mem_buf, + return gdb_get_reg64(mem_buf, env->active_fpu.fpr[n - 38].d); } else { return gdb_get_regl(mem_buf, @@ -100,6 +100,7 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) break; default: if (env->CP0_Status & (1 << CP0St_FR)) { + uint64_t tmp = ldq_p(mem_buf); env->active_fpu.fpr[n - 38].d = tmp; } else { env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;