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Hexagon (target/hexagon) Add overrides for loop setup instructions 

These instructions have implicit writes to registers, so we don't
want them to be helpers when idef-parser is off.

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-4-tsimpson@quicinc.com>
This commit is contained in:
Taylor Simpson 2023-04-27 15:59:54 -07:00
parent 07540a28c7
commit 17fda3c2d4
2 changed files with 65 additions and 0 deletions
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21
target/hexagon/gen_tcg.h
View File

@ -665,6 +665,27 @@
#define fGEN_TCG_J2_callrf(SHORTCODE) \
gen_cond_callr(ctx, TCG_COND_NE, PuV, RsV)
#define fGEN_TCG_J2_loop0r(SHORTCODE) \
gen_loop0r(ctx, RsV, riV)
#define fGEN_TCG_J2_loop1r(SHORTCODE) \
gen_loop1r(ctx, RsV, riV)
#define fGEN_TCG_J2_loop0i(SHORTCODE) \
gen_loop0i(ctx, UiV, riV)
#define fGEN_TCG_J2_loop1i(SHORTCODE) \
gen_loop1i(ctx, UiV, riV)
#define fGEN_TCG_J2_ploop1sr(SHORTCODE) \
gen_ploopNsr(ctx, 1, RsV, riV)
#define fGEN_TCG_J2_ploop1si(SHORTCODE) \
gen_ploopNsi(ctx, 1, UiV, riV)
#define fGEN_TCG_J2_ploop2sr(SHORTCODE) \
gen_ploopNsr(ctx, 2, RsV, riV)
#define fGEN_TCG_J2_ploop2si(SHORTCODE) \
gen_ploopNsi(ctx, 2, UiV, riV)
#define fGEN_TCG_J2_ploop3sr(SHORTCODE) \
gen_ploopNsr(ctx, 3, RsV, riV)
#define fGEN_TCG_J2_ploop3si(SHORTCODE) \
gen_ploopNsi(ctx, 3, UiV, riV)
#define fGEN_TCG_J2_endloop0(SHORTCODE) \
gen_endloop0(ctx)
#define fGEN_TCG_J2_endloop1(SHORTCODE) \

44
target/hexagon/genptr.c
View File

@ -518,6 +518,50 @@ static void gen_compare(TCGCond cond, TCGv res, TCGv arg1, TCGv arg2)
tcg_gen_movcond_tl(cond, res, arg1, arg2, one, zero);
}
#ifndef CONFIG_HEXAGON_IDEF_PARSER
static inline void gen_loop0r(DisasContext *ctx, TCGv RsV, int riV)
{
fIMMEXT(riV);
fPCALIGN(riV);
gen_log_reg_write(ctx, HEX_REG_LC0, RsV);
gen_log_reg_write(ctx, HEX_REG_SA0, tcg_constant_tl(ctx->pkt->pc + riV));
gen_set_usr_fieldi(ctx, USR_LPCFG, 0);
}
static void gen_loop0i(DisasContext *ctx, int count, int riV)
{
gen_loop0r(ctx, tcg_constant_tl(count), riV);
}
static inline void gen_loop1r(DisasContext *ctx, TCGv RsV, int riV)
{
fIMMEXT(riV);
fPCALIGN(riV);
gen_log_reg_write(ctx, HEX_REG_LC1, RsV);
gen_log_reg_write(ctx, HEX_REG_SA1, tcg_constant_tl(ctx->pkt->pc + riV));
}
static void gen_loop1i(DisasContext *ctx, int count, int riV)
{
gen_loop1r(ctx, tcg_constant_tl(count), riV);
}
static void gen_ploopNsr(DisasContext *ctx, int N, TCGv RsV, int riV)
{
fIMMEXT(riV);
fPCALIGN(riV);
gen_log_reg_write(ctx, HEX_REG_LC0, RsV);
gen_log_reg_write(ctx, HEX_REG_SA0, tcg_constant_tl(ctx->pkt->pc + riV));
gen_set_usr_fieldi(ctx, USR_LPCFG, N);
gen_log_pred_write(ctx, 3, tcg_constant_tl(0));
}
static void gen_ploopNsi(DisasContext *ctx, int N, int count, int riV)
{
gen_ploopNsr(ctx, N, tcg_constant_tl(count), riV);
}
#endif
static void gen_cond_jumpr(DisasContext *ctx, TCGv dst_pc,
TCGCond cond, TCGv pred)
{