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target/arm: Change gen_goto_tb to work on displacements 

In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221020030641.2066807-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-10-20 13:06:34 +10:00 committed by Peter Maydell
parent 8df8727973
commit 168122419e
2 changed files with 27 additions and 23 deletions
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40
target/arm/translate-a64.c
View File

@ -370,8 +370,10 @@ static inline bool use_goto_tb(DisasContext *s, uint64_t dest)
return translator_use_goto_tb(&s->base, dest); return translator_use_goto_tb(&s->base, dest);
} }
static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) static void gen_goto_tb(DisasContext *s, int n, int64_t diff)
{ {
uint64_t dest = s->pc_curr + diff;
if (use_goto_tb(s, dest)) { if (use_goto_tb(s, dest)) {
tcg_gen_goto_tb(n); tcg_gen_goto_tb(n);
gen_a64_set_pc_im(dest); gen_a64_set_pc_im(dest);
@ -1354,7 +1356,7 @@ static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table,
*/ */
static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
{ {
uint64_t addr = s->pc_curr + sextract32(insn, 0, 26) * 4; int64_t diff = sextract32(insn, 0, 26) * 4;
if (insn & (1U << 31)) { if (insn & (1U << 31)) {
/* BL Branch with link */ /* BL Branch with link */
@ -1363,7 +1365,7 @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
/* B Branch / BL Branch with link */ /* B Branch / BL Branch with link */
reset_btype(s); reset_btype(s);
gen_goto_tb(s, 0, addr); gen_goto_tb(s, 0, diff);
} }
/* Compare and branch (immediate) /* Compare and branch (immediate)
@ -1375,14 +1377,14 @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
static void disas_comp_b_imm(DisasContext *s, uint32_t insn) static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
{ {
unsigned int sf, op, rt; unsigned int sf, op, rt;
uint64_t addr; int64_t diff;
TCGLabel *label_match; TCGLabel *label_match;
TCGv_i64 tcg_cmp; TCGv_i64 tcg_cmp;
sf = extract32(insn, 31, 1); sf = extract32(insn, 31, 1);
op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */ op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */
rt = extract32(insn, 0, 5); rt = extract32(insn, 0, 5);
addr = s->pc_curr + sextract32(insn, 5, 19) * 4; diff = sextract32(insn, 5, 19) * 4;
tcg_cmp = read_cpu_reg(s, rt, sf); tcg_cmp = read_cpu_reg(s, rt, sf);
label_match = gen_new_label(); label_match = gen_new_label();
@ -1391,9 +1393,9 @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
tcg_cmp, 0, label_match); tcg_cmp, 0, label_match);
gen_goto_tb(s, 0, s->base.pc_next); gen_goto_tb(s, 0, 4);
gen_set_label(label_match); gen_set_label(label_match);
gen_goto_tb(s, 1, addr); gen_goto_tb(s, 1, diff);
} }
/* Test and branch (immediate) /* Test and branch (immediate)
@ -1405,13 +1407,13 @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
static void disas_test_b_imm(DisasContext *s, uint32_t insn) static void disas_test_b_imm(DisasContext *s, uint32_t insn)
{ {
unsigned int bit_pos, op, rt; unsigned int bit_pos, op, rt;
uint64_t addr; int64_t diff;
TCGLabel *label_match; TCGLabel *label_match;
TCGv_i64 tcg_cmp; TCGv_i64 tcg_cmp;
bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5);
op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */ op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */
addr = s->pc_curr + sextract32(insn, 5, 14) * 4; diff = sextract32(insn, 5, 14) * 4;
rt = extract32(insn, 0, 5); rt = extract32(insn, 0, 5);
tcg_cmp = tcg_temp_new_i64(); tcg_cmp = tcg_temp_new_i64();
@ -1422,9 +1424,9 @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn)
tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
tcg_cmp, 0, label_match); tcg_cmp, 0, label_match);
tcg_temp_free_i64(tcg_cmp); tcg_temp_free_i64(tcg_cmp);
gen_goto_tb(s, 0, s->base.pc_next); gen_goto_tb(s, 0, 4);
gen_set_label(label_match); gen_set_label(label_match);
gen_goto_tb(s, 1, addr); gen_goto_tb(s, 1, diff);
} }
/* Conditional branch (immediate) /* Conditional branch (immediate)
@ -1436,13 +1438,13 @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn)
static void disas_cond_b_imm(DisasContext *s, uint32_t insn) static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
{ {
unsigned int cond; unsigned int cond;
uint64_t addr; int64_t diff;
if ((insn & (1 << 4)) || (insn & (1 << 24))) { if ((insn & (1 << 4)) || (insn & (1 << 24))) {
unallocated_encoding(s); unallocated_encoding(s);
return; return;
} }
addr = s->pc_curr + sextract32(insn, 5, 19) * 4; diff = sextract32(insn, 5, 19) * 4;
cond = extract32(insn, 0, 4); cond = extract32(insn, 0, 4);
reset_btype(s); reset_btype(s);
@ -1450,12 +1452,12 @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
/* genuinely conditional branches */ /* genuinely conditional branches */
TCGLabel *label_match = gen_new_label(); TCGLabel *label_match = gen_new_label();
arm_gen_test_cc(cond, label_match); arm_gen_test_cc(cond, label_match);
gen_goto_tb(s, 0, s->base.pc_next); gen_goto_tb(s, 0, 4);
gen_set_label(label_match); gen_set_label(label_match);
gen_goto_tb(s, 1, addr); gen_goto_tb(s, 1, diff);
} else { } else {
/* 0xe and 0xf are both "always" conditions */ /* 0xe and 0xf are both "always" conditions */
gen_goto_tb(s, 0, addr); gen_goto_tb(s, 0, diff);
} }
} }
@ -1629,7 +1631,7 @@ static void handle_sync(DisasContext *s, uint32_t insn,
* any pending interrupts immediately. * any pending interrupts immediately.
*/ */
reset_btype(s); reset_btype(s);
gen_goto_tb(s, 0, s->base.pc_next); gen_goto_tb(s, 0, 4);
return; return;
case 7: /* SB */ case 7: /* SB */
@ -1641,7 +1643,7 @@ static void handle_sync(DisasContext *s, uint32_t insn,
* MB and end the TB instead. * MB and end the TB instead.
*/ */
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
gen_goto_tb(s, 0, s->base.pc_next); gen_goto_tb(s, 0, 4);
return; return;
default: default:
@ -14946,7 +14948,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
switch (dc->base.is_jmp) { switch (dc->base.is_jmp) {
case DISAS_NEXT: case DISAS_NEXT:
case DISAS_TOO_MANY: case DISAS_TOO_MANY:
gen_goto_tb(dc, 1, dc->base.pc_next); gen_goto_tb(dc, 1, 4);
break; break;
default: default:
case DISAS_UPDATE_EXIT: case DISAS_UPDATE_EXIT:

10
target/arm/translate.c
View File

@ -2590,8 +2590,10 @@ static void gen_goto_ptr(void)
* cpu_loop_exec. Any live exit_requests will be processed as we * cpu_loop_exec. Any live exit_requests will be processed as we
* enter the next TB. * enter the next TB.
*/ */
static void gen_goto_tb(DisasContext *s, int n, target_ulong dest) static void gen_goto_tb(DisasContext *s, int n, int diff)
{ {
target_ulong dest = s->pc_curr + diff;
if (translator_use_goto_tb(&s->base, dest)) { if (translator_use_goto_tb(&s->base, dest)) {
tcg_gen_goto_tb(n); tcg_gen_goto_tb(n);
gen_set_pc_im(s, dest); gen_set_pc_im(s, dest);
@ -2625,7 +2627,7 @@ static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
* gen_jmp(); * gen_jmp();
* on the second call to gen_jmp(). * on the second call to gen_jmp().
*/ */
gen_goto_tb(s, tbno, dest); gen_goto_tb(s, tbno, dest - s->pc_curr);
break; break;
case DISAS_UPDATE_NOCHAIN: case DISAS_UPDATE_NOCHAIN:
case DISAS_UPDATE_EXIT: case DISAS_UPDATE_EXIT:
@ -9793,7 +9795,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
switch (dc->base.is_jmp) { switch (dc->base.is_jmp) {
case DISAS_NEXT: case DISAS_NEXT:
case DISAS_TOO_MANY: case DISAS_TOO_MANY:
gen_goto_tb(dc, 1, dc->base.pc_next); gen_goto_tb(dc, 1, curr_insn_len(dc));
break; break;
case DISAS_UPDATE_NOCHAIN: case DISAS_UPDATE_NOCHAIN:
gen_set_pc_im(dc, dc->base.pc_next); gen_set_pc_im(dc, dc->base.pc_next);
@ -9845,7 +9847,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
gen_set_pc_im(dc, dc->base.pc_next); gen_set_pc_im(dc, dc->base.pc_next);
gen_singlestep_exception(dc); gen_singlestep_exception(dc);
} else { } else {
gen_goto_tb(dc, 1, dc->base.pc_next); gen_goto_tb(dc, 1, curr_insn_len(dc));
} }
} }
} }