mirror of https://github.com/xemu-project/xemu.git
target/loongarch: Implement vssrlrn vssrarn
This patch includes:
- VSSRLRN.{B.H/H.W/W.D};
- VSSRARN.{B.H/H.W/W.D};
- VSSRLRN.{BU.H/HU.W/WU.D};
- VSSRARN.{BU.H/HU.W/WU.D};
- VSSRLRNI.{B.H/H.W/W.D/D.Q};
- VSSRARNI.{B.H/H.W/W.D/D.Q};
- VSSRLRNI.{BU.H/HU.W/WU.D/DU.Q};
- VSSRARNI.{BU.H/HU.W/WU.D/DU.Q}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-29-gaosong@loongson.cn>
This commit is contained in:
Song Gao
parent
83b3815dbc
commit
162cd32cfe
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@ -1228,3 +1228,33 @@ INSN_LSX(vssrani_bu_h, vv_i)
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INSN_LSX(vssrani_hu_w, vv_i)
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INSN_LSX(vssrani_wu_d, vv_i)
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INSN_LSX(vssrani_du_q, vv_i)
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INSN_LSX(vssrlrn_b_h, vvv)
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INSN_LSX(vssrlrn_h_w, vvv)
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INSN_LSX(vssrlrn_w_d, vvv)
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INSN_LSX(vssrarn_b_h, vvv)
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INSN_LSX(vssrarn_h_w, vvv)
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INSN_LSX(vssrarn_w_d, vvv)
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INSN_LSX(vssrlrn_bu_h, vvv)
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INSN_LSX(vssrlrn_hu_w, vvv)
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INSN_LSX(vssrlrn_wu_d, vvv)
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INSN_LSX(vssrarn_bu_h, vvv)
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INSN_LSX(vssrarn_hu_w, vvv)
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INSN_LSX(vssrarn_wu_d, vvv)
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INSN_LSX(vssrlrni_b_h, vv_i)
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INSN_LSX(vssrlrni_h_w, vv_i)
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INSN_LSX(vssrlrni_w_d, vv_i)
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INSN_LSX(vssrlrni_d_q, vv_i)
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INSN_LSX(vssrlrni_bu_h, vv_i)
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INSN_LSX(vssrlrni_hu_w, vv_i)
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INSN_LSX(vssrlrni_wu_d, vv_i)
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INSN_LSX(vssrlrni_du_q, vv_i)
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INSN_LSX(vssrarni_b_h, vv_i)
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INSN_LSX(vssrarni_h_w, vv_i)
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INSN_LSX(vssrarni_w_d, vv_i)
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INSN_LSX(vssrarni_d_q, vv_i)
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INSN_LSX(vssrarni_bu_h, vv_i)
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INSN_LSX(vssrarni_hu_w, vv_i)
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INSN_LSX(vssrarni_wu_d, vv_i)
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INSN_LSX(vssrarni_du_q, vv_i)
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@ -441,3 +441,33 @@ DEF_HELPER_4(vssrani_bu_h, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrani_hu_w, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrani_wu_d, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrani_du_q, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrlrn_b_h, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrlrn_h_w, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrlrn_w_d, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrarn_b_h, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrarn_h_w, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrarn_w_d, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrlrn_bu_h, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrlrn_hu_w, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrlrn_wu_d, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrarn_bu_h, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrarn_hu_w, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrarn_wu_d, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrlrni_b_h, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrlrni_h_w, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrlrni_w_d, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrlrni_d_q, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrarni_b_h, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrarni_h_w, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrarni_w_d, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrarni_d_q, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrlrni_bu_h, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrlrni_hu_w, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrlrni_wu_d, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrlrni_du_q, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrarni_bu_h, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrarni_hu_w, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrarni_wu_d, void, env, i32, i32, i32)
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DEF_HELPER_4(vssrarni_du_q, void, env, i32, i32, i32)
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@ -3067,3 +3067,33 @@ TRANS(vssrani_bu_h, gen_vv_i, gen_helper_vssrani_bu_h)
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TRANS(vssrani_hu_w, gen_vv_i, gen_helper_vssrani_hu_w)
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TRANS(vssrani_wu_d, gen_vv_i, gen_helper_vssrani_wu_d)
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TRANS(vssrani_du_q, gen_vv_i, gen_helper_vssrani_du_q)
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TRANS(vssrlrn_b_h, gen_vvv, gen_helper_vssrlrn_b_h)
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TRANS(vssrlrn_h_w, gen_vvv, gen_helper_vssrlrn_h_w)
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TRANS(vssrlrn_w_d, gen_vvv, gen_helper_vssrlrn_w_d)
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TRANS(vssrarn_b_h, gen_vvv, gen_helper_vssrarn_b_h)
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TRANS(vssrarn_h_w, gen_vvv, gen_helper_vssrarn_h_w)
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TRANS(vssrarn_w_d, gen_vvv, gen_helper_vssrarn_w_d)
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TRANS(vssrlrn_bu_h, gen_vvv, gen_helper_vssrlrn_bu_h)
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TRANS(vssrlrn_hu_w, gen_vvv, gen_helper_vssrlrn_hu_w)
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TRANS(vssrlrn_wu_d, gen_vvv, gen_helper_vssrlrn_wu_d)
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TRANS(vssrarn_bu_h, gen_vvv, gen_helper_vssrarn_bu_h)
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TRANS(vssrarn_hu_w, gen_vvv, gen_helper_vssrarn_hu_w)
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TRANS(vssrarn_wu_d, gen_vvv, gen_helper_vssrarn_wu_d)
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TRANS(vssrlrni_b_h, gen_vv_i, gen_helper_vssrlrni_b_h)
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TRANS(vssrlrni_h_w, gen_vv_i, gen_helper_vssrlrni_h_w)
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TRANS(vssrlrni_w_d, gen_vv_i, gen_helper_vssrlrni_w_d)
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TRANS(vssrlrni_d_q, gen_vv_i, gen_helper_vssrlrni_d_q)
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TRANS(vssrarni_b_h, gen_vv_i, gen_helper_vssrarni_b_h)
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TRANS(vssrarni_h_w, gen_vv_i, gen_helper_vssrarni_h_w)
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TRANS(vssrarni_w_d, gen_vv_i, gen_helper_vssrarni_w_d)
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TRANS(vssrarni_d_q, gen_vv_i, gen_helper_vssrarni_d_q)
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TRANS(vssrlrni_bu_h, gen_vv_i, gen_helper_vssrlrni_bu_h)
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TRANS(vssrlrni_hu_w, gen_vv_i, gen_helper_vssrlrni_hu_w)
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TRANS(vssrlrni_wu_d, gen_vv_i, gen_helper_vssrlrni_wu_d)
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TRANS(vssrlrni_du_q, gen_vv_i, gen_helper_vssrlrni_du_q)
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TRANS(vssrarni_bu_h, gen_vv_i, gen_helper_vssrarni_bu_h)
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TRANS(vssrarni_hu_w, gen_vv_i, gen_helper_vssrarni_hu_w)
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TRANS(vssrarni_wu_d, gen_vv_i, gen_helper_vssrarni_wu_d)
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TRANS(vssrarni_du_q, gen_vv_i, gen_helper_vssrarni_du_q)
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@ -929,3 +929,33 @@ vssrani_bu_h 0111 00110110 01000 1 .... ..... ..... @vv_ui4
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vssrani_hu_w 0111 00110110 01001 ..... ..... ..... @vv_ui5
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vssrani_wu_d 0111 00110110 0101 ...... ..... ..... @vv_ui6
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vssrani_du_q 0111 00110110 011 ....... ..... ..... @vv_ui7
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vssrlrn_b_h 0111 00010000 00001 ..... ..... ..... @vvv
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vssrlrn_h_w 0111 00010000 00010 ..... ..... ..... @vvv
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vssrlrn_w_d 0111 00010000 00011 ..... ..... ..... @vvv
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vssrarn_b_h 0111 00010000 00101 ..... ..... ..... @vvv
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vssrarn_h_w 0111 00010000 00110 ..... ..... ..... @vvv
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vssrarn_w_d 0111 00010000 00111 ..... ..... ..... @vvv
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vssrlrn_bu_h 0111 00010000 10001 ..... ..... ..... @vvv
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vssrlrn_hu_w 0111 00010000 10010 ..... ..... ..... @vvv
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vssrlrn_wu_d 0111 00010000 10011 ..... ..... ..... @vvv
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vssrarn_bu_h 0111 00010000 10101 ..... ..... ..... @vvv
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vssrarn_hu_w 0111 00010000 10110 ..... ..... ..... @vvv
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vssrarn_wu_d 0111 00010000 10111 ..... ..... ..... @vvv
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vssrlrni_b_h 0111 00110101 00000 1 .... ..... ..... @vv_ui4
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vssrlrni_h_w 0111 00110101 00001 ..... ..... ..... @vv_ui5
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vssrlrni_w_d 0111 00110101 0001 ...... ..... ..... @vv_ui6
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vssrlrni_d_q 0111 00110101 001 ....... ..... ..... @vv_ui7
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vssrarni_b_h 0111 00110110 10000 1 .... ..... ..... @vv_ui4
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vssrarni_h_w 0111 00110110 10001 ..... ..... ..... @vv_ui5
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vssrarni_w_d 0111 00110110 1001 ...... ..... ..... @vv_ui6
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vssrarni_d_q 0111 00110110 101 ....... ..... ..... @vv_ui7
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vssrlrni_bu_h 0111 00110101 01000 1 .... ..... ..... @vv_ui4
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vssrlrni_hu_w 0111 00110101 01001 ..... ..... ..... @vv_ui5
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vssrlrni_wu_d 0111 00110101 0101 ...... ..... ..... @vv_ui6
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vssrlrni_du_q 0111 00110101 011 ....... ..... ..... @vv_ui7
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vssrarni_bu_h 0111 00110110 11000 1 .... ..... ..... @vv_ui4
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vssrarni_hu_w 0111 00110110 11001 ..... ..... ..... @vv_ui5
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vssrarni_wu_d 0111 00110110 1101 ...... ..... ..... @vv_ui6
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vssrarni_du_q 0111 00110110 111 ....... ..... ..... @vv_ui7
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@ -1557,3 +1557,361 @@ void HELPER(vssrani_du_q)(CPULoongArchState *env,
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VSSRANUI(vssrani_bu_h, 16, B, H)
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VSSRANUI(vssrani_hu_w, 32, H, W)
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VSSRANUI(vssrani_wu_d, 64, W, D)
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#define SSRLRNS(E1, E2, T1, T2, T3) \
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static T1 do_ssrlrns_ ## E1(T2 e2, int sa, int sh) \
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{ \
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T1 shft_res; \
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\
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shft_res = do_vsrlr_ ## E2(e2, sa); \
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T1 mask; \
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mask = (1ull << sh) -1; \
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if (shft_res > mask) { \
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return mask; \
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} else { \
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return shft_res; \
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} \
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}
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SSRLRNS(B, H, uint16_t, int16_t, uint8_t)
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SSRLRNS(H, W, uint32_t, int32_t, uint16_t)
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SSRLRNS(W, D, uint64_t, int64_t, uint32_t)
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#define VSSRLRN(NAME, BIT, T, E1, E2) \
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void HELPER(NAME)(CPULoongArchState *env, \
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uint32_t vd, uint32_t vj, uint32_t vk) \
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{ \
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int i; \
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VReg *Vd = &(env->fpr[vd].vreg); \
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VReg *Vj = &(env->fpr[vj].vreg); \
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VReg *Vk = &(env->fpr[vk].vreg); \
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\
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for (i = 0; i < LSX_LEN/BIT; i++) { \
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Vd->E1(i) = do_ssrlrns_ ## E1(Vj->E2(i), (T)Vk->E2(i)%BIT, BIT/2 -1); \
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} \
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Vd->D(1) = 0; \
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}
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VSSRLRN(vssrlrn_b_h, 16, uint16_t, B, H)
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VSSRLRN(vssrlrn_h_w, 32, uint32_t, H, W)
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VSSRLRN(vssrlrn_w_d, 64, uint64_t, W, D)
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#define SSRARNS(E1, E2, T1, T2) \
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static T1 do_ssrarns_ ## E1(T1 e2, int sa, int sh) \
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{ \
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T1 shft_res; \
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\
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shft_res = do_vsrar_ ## E2(e2, sa); \
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T2 mask; \
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mask = (1ll << sh) -1; \
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if (shft_res > mask) { \
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return mask; \
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} else if (shft_res < -(mask +1)) { \
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return ~mask; \
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} else { \
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return shft_res; \
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} \
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}
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SSRARNS(B, H, int16_t, int8_t)
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SSRARNS(H, W, int32_t, int16_t)
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SSRARNS(W, D, int64_t, int32_t)
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#define VSSRARN(NAME, BIT, T, E1, E2) \
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void HELPER(NAME)(CPULoongArchState *env, \
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uint32_t vd, uint32_t vj, uint32_t vk) \
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{ \
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int i; \
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VReg *Vd = &(env->fpr[vd].vreg); \
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VReg *Vj = &(env->fpr[vj].vreg); \
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VReg *Vk = &(env->fpr[vk].vreg); \
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\
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for (i = 0; i < LSX_LEN/BIT; i++) { \
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Vd->E1(i) = do_ssrarns_ ## E1(Vj->E2(i), (T)Vk->E2(i)%BIT, BIT/2 -1); \
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} \
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Vd->D(1) = 0; \
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}
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VSSRARN(vssrarn_b_h, 16, uint16_t, B, H)
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VSSRARN(vssrarn_h_w, 32, uint32_t, H, W)
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VSSRARN(vssrarn_w_d, 64, uint64_t, W, D)
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#define SSRLRNU(E1, E2, T1, T2, T3) \
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static T1 do_ssrlrnu_ ## E1(T3 e2, int sa, int sh) \
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{ \
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T1 shft_res; \
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\
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shft_res = do_vsrlr_ ## E2(e2, sa); \
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\
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T2 mask; \
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mask = (1ull << sh) -1; \
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if (shft_res > mask) { \
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return mask; \
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} else { \
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return shft_res; \
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} \
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}
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SSRLRNU(B, H, uint16_t, uint8_t, int16_t)
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SSRLRNU(H, W, uint32_t, uint16_t, int32_t)
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SSRLRNU(W, D, uint64_t, uint32_t, int64_t)
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#define VSSRLRNU(NAME, BIT, T, E1, E2) \
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void HELPER(NAME)(CPULoongArchState *env, \
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uint32_t vd, uint32_t vj, uint32_t vk) \
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{ \
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int i; \
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VReg *Vd = &(env->fpr[vd].vreg); \
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VReg *Vj = &(env->fpr[vj].vreg); \
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VReg *Vk = &(env->fpr[vk].vreg); \
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\
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for (i = 0; i < LSX_LEN/BIT; i++) { \
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Vd->E1(i) = do_ssrlrnu_ ## E1(Vj->E2(i), (T)Vk->E2(i)%BIT, BIT/2); \
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} \
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Vd->D(1) = 0; \
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}
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VSSRLRNU(vssrlrn_bu_h, 16, uint16_t, B, H)
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VSSRLRNU(vssrlrn_hu_w, 32, uint32_t, H, W)
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VSSRLRNU(vssrlrn_wu_d, 64, uint64_t, W, D)
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#define SSRARNU(E1, E2, T1, T2, T3) \
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static T1 do_ssrarnu_ ## E1(T3 e2, int sa, int sh) \
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{ \
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T1 shft_res; \
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\
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if (e2 < 0) { \
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shft_res = 0; \
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} else { \
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shft_res = do_vsrar_ ## E2(e2, sa); \
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} \
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T2 mask; \
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mask = (1ull << sh) -1; \
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if (shft_res > mask) { \
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return mask; \
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} else { \
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return shft_res; \
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} \
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}
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SSRARNU(B, H, uint16_t, uint8_t, int16_t)
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SSRARNU(H, W, uint32_t, uint16_t, int32_t)
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SSRARNU(W, D, uint64_t, uint32_t, int64_t)
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#define VSSRARNU(NAME, BIT, T, E1, E2) \
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void HELPER(NAME)(CPULoongArchState *env, \
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uint32_t vd, uint32_t vj, uint32_t vk) \
|
||||
{ \
|
||||
int i; \
|
||||
VReg *Vd = &(env->fpr[vd].vreg); \
|
||||
VReg *Vj = &(env->fpr[vj].vreg); \
|
||||
VReg *Vk = &(env->fpr[vk].vreg); \
|
||||
\
|
||||
for (i = 0; i < LSX_LEN/BIT; i++) { \
|
||||
Vd->E1(i) = do_ssrarnu_ ## E1(Vj->E2(i), (T)Vk->E2(i)%BIT, BIT/2); \
|
||||
} \
|
||||
Vd->D(1) = 0; \
|
||||
}
|
||||
|
||||
VSSRARNU(vssrarn_bu_h, 16, uint16_t, B, H)
|
||||
VSSRARNU(vssrarn_hu_w, 32, uint32_t, H, W)
|
||||
VSSRARNU(vssrarn_wu_d, 64, uint64_t, W, D)
|
||||
|
||||
#define VSSRLRNI(NAME, BIT, E1, E2) \
|
||||
void HELPER(NAME)(CPULoongArchState *env, \
|
||||
uint32_t vd, uint32_t vj, uint32_t imm) \
|
||||
{ \
|
||||
int i; \
|
||||
VReg temp; \
|
||||
VReg *Vd = &(env->fpr[vd].vreg); \
|
||||
VReg *Vj = &(env->fpr[vj].vreg); \
|
||||
\
|
||||
for (i = 0; i < LSX_LEN/BIT; i++) { \
|
||||
temp.E1(i) = do_ssrlrns_ ## E1(Vj->E2(i), imm, BIT/2 -1); \
|
||||
temp.E1(i + LSX_LEN/BIT) = do_ssrlrns_ ## E1(Vd->E2(i), imm, BIT/2 -1);\
|
||||
} \
|
||||
*Vd = temp; \
|
||||
}
|
||||
|
||||
#define VSSRLRNI_Q(NAME, sh) \
|
||||
void HELPER(NAME)(CPULoongArchState *env, \
|
||||
uint32_t vd, uint32_t vj, uint32_t imm) \
|
||||
{ \
|
||||
Int128 shft_res1, shft_res2, mask, r1, r2; \
|
||||
VReg *Vd = &(env->fpr[vd].vreg); \
|
||||
VReg *Vj = &(env->fpr[vj].vreg); \
|
||||
\
|
||||
if (imm == 0) { \
|
||||
shft_res1 = Vj->Q(0); \
|
||||
shft_res2 = Vd->Q(0); \
|
||||
} else { \
|
||||
r1 = int128_and(int128_urshift(Vj->Q(0), (imm -1)), int128_one()); \
|
||||
r2 = int128_and(int128_urshift(Vd->Q(0), (imm -1)), int128_one()); \
|
||||
\
|
||||
shft_res1 = (int128_add(int128_urshift(Vj->Q(0), imm), r1)); \
|
||||
shft_res2 = (int128_add(int128_urshift(Vd->Q(0), imm), r2)); \
|
||||
} \
|
||||
\
|
||||
mask = int128_sub(int128_lshift(int128_one(), sh), int128_one()); \
|
||||
\
|
||||
if (int128_ult(mask, shft_res1)) { \
|
||||
Vd->D(0) = int128_getlo(mask); \
|
||||
}else { \
|
||||
Vd->D(0) = int128_getlo(shft_res1); \
|
||||
} \
|
||||
\
|
||||
if (int128_ult(mask, shft_res2)) { \
|
||||
Vd->D(1) = int128_getlo(mask); \
|
||||
}else { \
|
||||
Vd->D(1) = int128_getlo(shft_res2); \
|
||||
} \
|
||||
}
|
||||
|
||||
VSSRLRNI(vssrlrni_b_h, 16, B, H)
|
||||
VSSRLRNI(vssrlrni_h_w, 32, H, W)
|
||||
VSSRLRNI(vssrlrni_w_d, 64, W, D)
|
||||
VSSRLRNI_Q(vssrlrni_d_q, 63)
|
||||
|
||||
#define VSSRARNI(NAME, BIT, E1, E2) \
|
||||
void HELPER(NAME)(CPULoongArchState *env, \
|
||||
uint32_t vd, uint32_t vj, uint32_t imm) \
|
||||
{ \
|
||||
int i; \
|
||||
VReg temp; \
|
||||
VReg *Vd = &(env->fpr[vd].vreg); \
|
||||
VReg *Vj = &(env->fpr[vj].vreg); \
|
||||
\
|
||||
for (i = 0; i < LSX_LEN/BIT; i++) { \
|
||||
temp.E1(i) = do_ssrarns_ ## E1(Vj->E2(i), imm, BIT/2 -1); \
|
||||
temp.E1(i + LSX_LEN/BIT) = do_ssrarns_ ## E1(Vd->E2(i), imm, BIT/2 -1); \
|
||||
} \
|
||||
*Vd = temp; \
|
||||
}
|
||||
|
||||
void HELPER(vssrarni_d_q)(CPULoongArchState *env,
|
||||
uint32_t vd, uint32_t vj, uint32_t imm)
|
||||
{
|
||||
Int128 shft_res1, shft_res2, mask1, mask2, r1, r2;
|
||||
VReg *Vd = &(env->fpr[vd].vreg);
|
||||
VReg *Vj = &(env->fpr[vj].vreg);
|
||||
|
||||
if (imm == 0) {
|
||||
shft_res1 = Vj->Q(0);
|
||||
shft_res2 = Vd->Q(0);
|
||||
} else {
|
||||
r1 = int128_and(int128_rshift(Vj->Q(0), (imm -1)), int128_one());
|
||||
r2 = int128_and(int128_rshift(Vd->Q(0), (imm -1)), int128_one());
|
||||
|
||||
shft_res1 = int128_add(int128_rshift(Vj->Q(0), imm), r1);
|
||||
shft_res2 = int128_add(int128_rshift(Vd->Q(0), imm), r2);
|
||||
}
|
||||
|
||||
mask1 = int128_sub(int128_lshift(int128_one(), 63), int128_one());
|
||||
mask2 = int128_lshift(int128_one(), 63);
|
||||
|
||||
if (int128_gt(shft_res1, mask1)) {
|
||||
Vd->D(0) = int128_getlo(mask1);
|
||||
} else if (int128_lt(shft_res1, int128_neg(mask2))) {
|
||||
Vd->D(0) = int128_getlo(mask2);
|
||||
} else {
|
||||
Vd->D(0) = int128_getlo(shft_res1);
|
||||
}
|
||||
|
||||
if (int128_gt(shft_res2, mask1)) {
|
||||
Vd->D(1) = int128_getlo(mask1);
|
||||
} else if (int128_lt(shft_res2, int128_neg(mask2))) {
|
||||
Vd->D(1) = int128_getlo(mask2);
|
||||
} else {
|
||||
Vd->D(1) = int128_getlo(shft_res2);
|
||||
}
|
||||
}
|
||||
|
||||
VSSRARNI(vssrarni_b_h, 16, B, H)
|
||||
VSSRARNI(vssrarni_h_w, 32, H, W)
|
||||
VSSRARNI(vssrarni_w_d, 64, W, D)
|
||||
|
||||
#define VSSRLRNUI(NAME, BIT, E1, E2) \
|
||||
void HELPER(NAME)(CPULoongArchState *env, \
|
||||
uint32_t vd, uint32_t vj, uint32_t imm) \
|
||||
{ \
|
||||
int i; \
|
||||
VReg temp; \
|
||||
VReg *Vd = &(env->fpr[vd].vreg); \
|
||||
VReg *Vj = &(env->fpr[vj].vreg); \
|
||||
\
|
||||
for (i = 0; i < LSX_LEN/BIT; i++) { \
|
||||
temp.E1(i) = do_ssrlrnu_ ## E1(Vj->E2(i), imm, BIT/2); \
|
||||
temp.E1(i + LSX_LEN/BIT) = do_ssrlrnu_ ## E1(Vd->E2(i), imm, BIT/2); \
|
||||
} \
|
||||
*Vd = temp; \
|
||||
}
|
||||
|
||||
VSSRLRNUI(vssrlrni_bu_h, 16, B, H)
|
||||
VSSRLRNUI(vssrlrni_hu_w, 32, H, W)
|
||||
VSSRLRNUI(vssrlrni_wu_d, 64, W, D)
|
||||
VSSRLRNI_Q(vssrlrni_du_q, 64)
|
||||
|
||||
#define VSSRARNUI(NAME, BIT, E1, E2) \
|
||||
void HELPER(NAME)(CPULoongArchState *env, \
|
||||
uint32_t vd, uint32_t vj, uint32_t imm) \
|
||||
{ \
|
||||
int i; \
|
||||
VReg temp; \
|
||||
VReg *Vd = &(env->fpr[vd].vreg); \
|
||||
VReg *Vj = &(env->fpr[vj].vreg); \
|
||||
\
|
||||
for (i = 0; i < LSX_LEN/BIT; i++) { \
|
||||
temp.E1(i) = do_ssrarnu_ ## E1(Vj->E2(i), imm, BIT/2); \
|
||||
temp.E1(i + LSX_LEN/BIT) = do_ssrarnu_ ## E1(Vd->E2(i), imm, BIT/2); \
|
||||
} \
|
||||
*Vd = temp; \
|
||||
}
|
||||
|
||||
void HELPER(vssrarni_du_q)(CPULoongArchState *env,
|
||||
uint32_t vd, uint32_t vj, uint32_t imm)
|
||||
{
|
||||
Int128 shft_res1, shft_res2, mask1, mask2, r1, r2;
|
||||
VReg *Vd = &(env->fpr[vd].vreg);
|
||||
VReg *Vj = &(env->fpr[vj].vreg);
|
||||
|
||||
if (imm == 0) {
|
||||
shft_res1 = Vj->Q(0);
|
||||
shft_res2 = Vd->Q(0);
|
||||
} else {
|
||||
r1 = int128_and(int128_rshift(Vj->Q(0), (imm -1)), int128_one());
|
||||
r2 = int128_and(int128_rshift(Vd->Q(0), (imm -1)), int128_one());
|
||||
|
||||
shft_res1 = int128_add(int128_rshift(Vj->Q(0), imm), r1);
|
||||
shft_res2 = int128_add(int128_rshift(Vd->Q(0), imm), r2);
|
||||
}
|
||||
|
||||
if (int128_lt(Vj->Q(0), int128_zero())) {
|
||||
shft_res1 = int128_zero();
|
||||
}
|
||||
if (int128_lt(Vd->Q(0), int128_zero())) {
|
||||
shft_res2 = int128_zero();
|
||||
}
|
||||
|
||||
mask1 = int128_sub(int128_lshift(int128_one(), 64), int128_one());
|
||||
mask2 = int128_lshift(int128_one(), 64);
|
||||
|
||||
if (int128_gt(shft_res1, mask1)) {
|
||||
Vd->D(0) = int128_getlo(mask1);
|
||||
} else if (int128_lt(shft_res1, int128_neg(mask2))) {
|
||||
Vd->D(0) = int128_getlo(mask2);
|
||||
} else {
|
||||
Vd->D(0) = int128_getlo(shft_res1);
|
||||
}
|
||||
|
||||
if (int128_gt(shft_res2, mask1)) {
|
||||
Vd->D(1) = int128_getlo(mask1);
|
||||
} else if (int128_lt(shft_res2, int128_neg(mask2))) {
|
||||
Vd->D(1) = int128_getlo(mask2);
|
||||
} else {
|
||||
Vd->D(1) = int128_getlo(shft_res2);
|
||||
}
|
||||
}
|
||||
|
||||
VSSRARNUI(vssrarni_bu_h, 16, B, H)
|
||||
VSSRARNUI(vssrarni_hu_w, 32, H, W)
|
||||
VSSRARNUI(vssrarni_wu_d, 64, W, D)
|
||||
|
|
|
|||
Loading…
Reference in New Issue