mirror of https://github.com/xemu-project/xemu.git
target/riscv: Validate misa_mxl_max only once
misa_mxl_max is now a class member and initialized only once for each class. This also moves the initialization of gdb_core_xml_file which will be referenced before realization in the future. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240203-riscv-v11-3-a23f4848a628@daynix.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -1349,6 +1349,26 @@ static const MISAExtInfo misa_ext_info_arr[] = {
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MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
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};
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static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
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{
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CPUClass *cc = CPU_CLASS(mcc);
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/* Validate that MISA_MXL is set properly. */
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switch (mcc->misa_mxl_max) {
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#ifdef TARGET_RISCV64
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case MXL_RV64:
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case MXL_RV128:
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cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
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break;
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#endif
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case MXL_RV32:
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cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
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break;
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default:
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g_assert_not_reached();
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}
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}
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static int riscv_validate_misa_info_idx(uint32_t bit)
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{
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int idx;
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@ -2309,6 +2329,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
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RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
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mcc->misa_mxl_max = (uint32_t)(uintptr_t)data;
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riscv_cpu_validate_misa_mxl(mcc);
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}
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static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
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@ -268,27 +268,6 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
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}
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}
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static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu)
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{
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RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
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CPUClass *cc = CPU_CLASS(mcc);
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/* Validate that MISA_MXL is set properly. */
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switch (mcc->misa_mxl_max) {
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#ifdef TARGET_RISCV64
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case MXL_RV64:
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case MXL_RV128:
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cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
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break;
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#endif
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case MXL_RV32:
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cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
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break;
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default:
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g_assert_not_reached();
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}
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}
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static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
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Error **errp)
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{
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@ -911,8 +890,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp)
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return false;
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}
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riscv_cpu_validate_misa_mxl(cpu);
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#ifndef CONFIG_USER_ONLY
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CPURISCVState *env = &cpu->env;
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Error *local_err = NULL;
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