mirror of https://github.com/xemu-project/xemu.git
target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP
Instead of clearing mask in riscv_cpu_update_mip() for VSTIP, we
should call riscv_cpu_update_mip() with mask == 0 from timer_helper.c
for VSTIP.
Fixes: 3ec0fe18a3
("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230120125950.2246378-3-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -621,8 +621,6 @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value)
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vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
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}
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/* No need to update mip for VSTIP */
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mask = ((mask == MIP_VSTIP) && env->vstime_irq) ? 0 : mask;
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vstip = env->vstime_irq ? MIP_VSTIP : 0;
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QEMU_IOTHREAD_LOCK_GUARD();
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@ -27,7 +27,7 @@ static void riscv_vstimer_cb(void *opaque)
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RISCVCPU *cpu = opaque;
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CPURISCVState *env = &cpu->env;
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env->vstime_irq = 1;
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riscv_cpu_update_mip(cpu, MIP_VSTIP, BOOL_TO_MASK(1));
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riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1));
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}
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static void riscv_stimer_cb(void *opaque)
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@ -57,16 +57,20 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
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*/
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if (timer_irq == MIP_VSTIP) {
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env->vstime_irq = 1;
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riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1));
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} else {
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riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1));
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}
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riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(1));
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return;
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}
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/* Clear the [VS|S]TIP bit in mip */
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if (timer_irq == MIP_VSTIP) {
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env->vstime_irq = 0;
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riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(0));
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} else {
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riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0));
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}
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/* Clear the [V]STIP bit in mip */
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riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0));
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/* otherwise, set up the future timer interrupt */
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diff = timecmp - rtc_r;
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