mirror of https://github.com/xemu-project/xemu.git
hw/i386/pc: Extract the x86 generic fw_cfg code
Extract all the functions that are not PC-machine specific into the (arch-specific) fw_cfg.c file. This will allow other X86-machine to reuse these functions. Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-16-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Philippe Mathieu-Daudé
Paolo Bonzini
parent
367607f913
commit
149c50cabc
137
hw/i386/fw_cfg.c
137
hw/i386/fw_cfg.c
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@ -13,8 +13,15 @@
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*/
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*/
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#include "qemu/osdep.h"
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#include "qemu/osdep.h"
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#include "sysemu/numa.h"
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#include "hw/acpi/acpi.h"
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#include "hw/firmware/smbios.h"
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#include "hw/i386/pc.h"
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#include "hw/i386/fw_cfg.h"
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#include "hw/i386/fw_cfg.h"
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#include "hw/timer/hpet.h"
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#include "hw/nvram/fw_cfg.h"
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#include "hw/nvram/fw_cfg.h"
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#include "e820_memory_layout.h"
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#include "kvm_i386.h"
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const char *fw_cfg_arch_key_name(uint16_t key)
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const char *fw_cfg_arch_key_name(uint16_t key)
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{
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{
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@ -36,3 +43,133 @@ const char *fw_cfg_arch_key_name(uint16_t key)
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}
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}
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return NULL;
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return NULL;
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}
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}
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void fw_cfg_build_smbios(MachineState *ms, FWCfgState *fw_cfg)
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{
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uint8_t *smbios_tables, *smbios_anchor;
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size_t smbios_tables_len, smbios_anchor_len;
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struct smbios_phys_mem_area *mem_array;
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unsigned i, array_count;
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X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
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/* tell smbios about cpuid version and features */
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smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
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smbios_tables = smbios_get_table_legacy(ms, &smbios_tables_len);
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if (smbios_tables) {
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fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
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smbios_tables, smbios_tables_len);
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}
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/* build the array of physical mem area from e820 table */
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mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
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for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
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uint64_t addr, len;
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if (e820_get_entry(i, E820_RAM, &addr, &len)) {
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mem_array[array_count].address = addr;
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mem_array[array_count].length = len;
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array_count++;
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}
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}
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smbios_get_tables(ms, mem_array, array_count,
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&smbios_tables, &smbios_tables_len,
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&smbios_anchor, &smbios_anchor_len);
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g_free(mem_array);
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if (smbios_anchor) {
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fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables",
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smbios_tables, smbios_tables_len);
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fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor",
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smbios_anchor, smbios_anchor_len);
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}
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}
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FWCfgState *fw_cfg_arch_create(MachineState *ms,
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uint16_t boot_cpus,
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uint16_t apic_id_limit)
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{
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FWCfgState *fw_cfg;
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uint64_t *numa_fw_cfg;
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int i;
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MachineClass *mc = MACHINE_GET_CLASS(ms);
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const CPUArchIdList *cpus = mc->possible_cpu_arch_ids(ms);
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int nb_numa_nodes = ms->numa_state->num_nodes;
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fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4,
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&address_space_memory);
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fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, boot_cpus);
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/* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
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*
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* For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
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* building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
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* that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
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* for CPU hotplug also uses APIC ID and not "CPU index".
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* This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
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* but the "limit to the APIC ID values SeaBIOS may see".
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*
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* So for compatibility reasons with old BIOSes we are stuck with
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* "etc/max-cpus" actually being apic_id_limit
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*/
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fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, apic_id_limit);
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fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
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fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
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acpi_tables, acpi_tables_len);
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fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
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fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
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&e820_reserve, sizeof(e820_reserve));
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fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
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sizeof(struct e820_entry) * e820_get_num_entries());
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fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
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/* allocate memory for the NUMA channel: one (64bit) word for the number
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* of nodes, one word for each VCPU->node and one word for each node to
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* hold the amount of memory.
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*/
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numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes);
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numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
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for (i = 0; i < cpus->len; i++) {
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unsigned int apic_id = cpus->cpus[i].arch_id;
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assert(apic_id < apic_id_limit);
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numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
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}
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for (i = 0; i < nb_numa_nodes; i++) {
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numa_fw_cfg[apic_id_limit + 1 + i] =
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cpu_to_le64(ms->numa_state->nodes[i].node_mem);
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}
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fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
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(1 + apic_id_limit + nb_numa_nodes) *
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sizeof(*numa_fw_cfg));
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return fw_cfg;
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}
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void fw_cfg_build_feature_control(MachineState *ms, FWCfgState *fw_cfg)
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{
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X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
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CPUX86State *env = &cpu->env;
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uint32_t unused, ecx, edx;
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uint64_t feature_control_bits = 0;
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uint64_t *val;
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cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
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if (ecx & CPUID_EXT_VMX) {
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feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
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}
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if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
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(CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
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(env->mcg_cap & MCG_LMCE_P)) {
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feature_control_bits |= FEATURE_CONTROL_LMCE;
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}
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if (!feature_control_bits) {
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return;
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}
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val = g_malloc(sizeof(*val));
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*val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
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fw_cfg_add_file(fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
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}
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@ -9,6 +9,7 @@
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#ifndef HW_I386_FW_CFG_H
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#ifndef HW_I386_FW_CFG_H
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#define HW_I386_FW_CFG_H
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#define HW_I386_FW_CFG_H
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#include "hw/boards.h"
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#include "hw/nvram/fw_cfg.h"
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#include "hw/nvram/fw_cfg.h"
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#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
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#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
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@ -17,4 +18,10 @@
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#define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
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#define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
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#define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
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#define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
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FWCfgState *fw_cfg_arch_create(MachineState *ms,
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uint16_t boot_cpus,
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uint16_t apic_id_limit);
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void fw_cfg_build_smbios(MachineState *ms, FWCfgState *fw_cfg);
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void fw_cfg_build_feature_control(MachineState *ms, FWCfgState *fw_cfg);
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#endif
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#endif
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132
hw/i386/pc.c
132
hw/i386/pc.c
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@ -88,6 +88,7 @@
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#include "qapi/qmp/qerror.h"
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#include "qapi/qmp/qerror.h"
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#include "config-devices.h"
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#include "config-devices.h"
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#include "e820_memory_layout.h"
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#include "e820_memory_layout.h"
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#include "fw_cfg.h"
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/* debug PC/ISA interrupts */
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/* debug PC/ISA interrupts */
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//#define DEBUG_IRQ
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//#define DEBUG_IRQ
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@ -894,108 +895,6 @@ static uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms,
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}
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}
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}
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}
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static void fw_cfg_build_smbios(MachineState *ms, FWCfgState *fw_cfg)
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{
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uint8_t *smbios_tables, *smbios_anchor;
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size_t smbios_tables_len, smbios_anchor_len;
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struct smbios_phys_mem_area *mem_array;
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unsigned i, array_count;
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X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
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/* tell smbios about cpuid version and features */
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smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
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smbios_tables = smbios_get_table_legacy(ms, &smbios_tables_len);
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if (smbios_tables) {
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fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
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smbios_tables, smbios_tables_len);
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}
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/* build the array of physical mem area from e820 table */
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mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
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for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
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uint64_t addr, len;
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if (e820_get_entry(i, E820_RAM, &addr, &len)) {
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mem_array[array_count].address = addr;
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mem_array[array_count].length = len;
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array_count++;
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}
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}
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smbios_get_tables(ms, mem_array, array_count,
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&smbios_tables, &smbios_tables_len,
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&smbios_anchor, &smbios_anchor_len);
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g_free(mem_array);
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if (smbios_anchor) {
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fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables",
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smbios_tables, smbios_tables_len);
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fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor",
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smbios_anchor, smbios_anchor_len);
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}
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}
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static FWCfgState *fw_cfg_arch_create(MachineState *ms,
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uint16_t boot_cpus,
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uint16_t apic_id_limit)
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{
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FWCfgState *fw_cfg;
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uint64_t *numa_fw_cfg;
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int i;
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MachineClass *mc = MACHINE_GET_CLASS(ms);
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const CPUArchIdList *cpus = mc->possible_cpu_arch_ids(ms);
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int nb_numa_nodes = ms->numa_state->num_nodes;
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fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4,
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&address_space_memory);
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fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, boot_cpus);
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/* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
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*
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* For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
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* building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
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* that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
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* for CPU hotplug also uses APIC ID and not "CPU index".
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* This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
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* but the "limit to the APIC ID values SeaBIOS may see".
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*
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* So for compatibility reasons with old BIOSes we are stuck with
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* "etc/max-cpus" actually being apic_id_limit
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*/
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fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, apic_id_limit);
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fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
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fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
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acpi_tables, acpi_tables_len);
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fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
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fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
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&e820_reserve, sizeof(e820_reserve));
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fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
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sizeof(struct e820_entry) * e820_get_num_entries());
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fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
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/* allocate memory for the NUMA channel: one (64bit) word for the number
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* of nodes, one word for each VCPU->node and one word for each node to
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* hold the amount of memory.
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*/
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numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes);
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numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
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for (i = 0; i < cpus->len; i++) {
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unsigned int apic_id = cpus->cpus[i].arch_id;
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assert(apic_id < apic_id_limit);
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numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
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}
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for (i = 0; i < nb_numa_nodes; i++) {
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numa_fw_cfg[apic_id_limit + 1 + i] =
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cpu_to_le64(ms->numa_state->nodes[i].node_mem);
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}
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fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
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(1 + apic_id_limit + nb_numa_nodes) *
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sizeof(*numa_fw_cfg));
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return fw_cfg;
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}
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static long get_file_size(FILE *f)
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static long get_file_size(FILE *f)
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{
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{
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long where, size;
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long where, size;
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@ -1623,35 +1522,6 @@ void pc_cpus_init(PCMachineState *pcms)
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}
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}
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}
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}
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static void fw_cfg_build_feature_control(MachineState *ms,
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FWCfgState *fw_cfg)
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{
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X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
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CPUX86State *env = &cpu->env;
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uint32_t unused, ecx, edx;
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uint64_t feature_control_bits = 0;
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|
||||||
uint64_t *val;
|
|
||||||
|
|
||||||
cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
|
|
||||||
if (ecx & CPUID_EXT_VMX) {
|
|
||||||
feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
|
|
||||||
}
|
|
||||||
|
|
||||||
if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
|
|
||||||
(CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
|
|
||||||
(env->mcg_cap & MCG_LMCE_P)) {
|
|
||||||
feature_control_bits |= FEATURE_CONTROL_LMCE;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!feature_control_bits) {
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
val = g_malloc(sizeof(*val));
|
|
||||||
*val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
|
|
||||||
fw_cfg_add_file(fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
|
|
||||||
}
|
|
||||||
|
|
||||||
static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
|
static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
|
||||||
{
|
{
|
||||||
if (cpus_count > 0xff) {
|
if (cpus_count > 0xff) {
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue