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target/ppc: enable PMU counter overflow with cycle events 

The PowerISA v3.1 defines that if the proper bits are set (MMCR0_PMC1CE
for PMC1 and MMCR0_PMCjCE for the remaining PMCs), counter negative
conditions are enabled. This means that if the counter value overflows
(i.e. exceeds 0x80000000) a performance monitor alert will occur. This alert
can trigger an event-based exception (to be implemented in the next patches)
if the MMCR0_EBE bit is set.

For now, overflowing the counter when the PMC is counting cycles will
just trigger a performance monitor alert. This is done by starting the
overflow timer to expire in the moment the overflow would be occuring. The
timer will call fire_PMC_interrupt() (via cpu_ppc_pmu_timer_cb) which will
trigger the PMU alert and, if the conditions are met, an EBB exception.

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-6-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Daniel Henrique Barboza 2021-12-17 17:57:18 +01:00 committed by Cédric Le Goater
parent a6f91249e0
commit 1474ba6d10
2 changed files with 73 additions and 0 deletions
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2
target/ppc/cpu.h
View File

@ -363,6 +363,8 @@ typedef enum {
#define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */
#define MMCR0_FC14 PPC_BIT(58) /* PMC Freeze Counters 1-4 bit */
#define MMCR0_FC56 PPC_BIT(59) /* PMC Freeze Counters 5-6 bit */
#define MMCR0_PMC1CE PPC_BIT(48) /* MMCR0 PMC1 Condition Enabled */
#define MMCR0_PMCjCE PPC_BIT(49) /* MMCR0 PMCj Condition Enabled */
/* MMCR0 userspace r/w mask */
#define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE)
/* MMCR2 userspace r/w mask */

71
target/ppc/power8-pmu.c
View File

@ -23,6 +23,8 @@
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
#define PMC_COUNTER_NEGATIVE_VAL 0x80000000UL
static bool pmc_is_inactive(CPUPPCState *env, int sprn)
{
if (env->spr[SPR_POWER_MMCR0] & MMCR0_FC) {
@ -36,6 +38,15 @@ static bool pmc_is_inactive(CPUPPCState *env, int sprn)
return env->spr[SPR_POWER_MMCR0] & MMCR0_FC56;
}
static bool pmc_has_overflow_enabled(CPUPPCState *env, int sprn)
{
if (sprn == SPR_POWER_PMC1) {
return env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE;
}
return env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE;
}
/*
* For PMCs 1-4, IBM POWER chips has support for an implementation
* dependent event, 0x1E, that enables cycle counting. The Linux kernel
@ -123,6 +134,61 @@ static void pmu_update_cycles(CPUPPCState *env)
env->pmu_base_time = now;
}
/*
* Helper function to retrieve the cycle overflow timer of the
* 'sprn' counter.
*/
static QEMUTimer *get_cyc_overflow_timer(CPUPPCState *env, int sprn)
{
return env->pmu_cyc_overflow_timers[sprn - SPR_POWER_PMC1];
}
static void pmc_update_overflow_timer(CPUPPCState *env, int sprn)
{
QEMUTimer *pmc_overflow_timer = get_cyc_overflow_timer(env, sprn);
int64_t timeout;
/*
* PMC5 does not have an overflow timer and this pointer
* will be NULL.
*/
if (!pmc_overflow_timer) {
return;
}
if (pmc_get_event(env, sprn) != PMU_EVENT_CYCLES ||
!pmc_has_overflow_enabled(env, sprn)) {
/* Overflow timer is not needed for this counter */
timer_del(pmc_overflow_timer);
return;
}
if (env->spr[sprn] >= PMC_COUNTER_NEGATIVE_VAL) {
timeout = 0;
} else {
timeout = PMC_COUNTER_NEGATIVE_VAL - env->spr[sprn];
}
/*
* Use timer_mod_anticipate() because an overflow timer might
* be already running for this PMC.
*/
timer_mod_anticipate(pmc_overflow_timer, env->pmu_base_time + timeout);
}
static void pmu_update_overflow_timers(CPUPPCState *env)
{
int sprn;
/*
* Scroll through all PMCs and start counter overflow timers for
* PM_CYC events, if needed.
*/
for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC6; sprn++) {
pmc_update_overflow_timer(env, sprn);
}
}
void helper_store_mmcr0(CPUPPCState *env, target_ulong value)
{
pmu_update_cycles(env);
@ -131,6 +197,9 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong value)
/* MMCR0 writes can change HFLAGS_PMCCCLEAR */
hreg_compute_hflags(env);
/* Update cycle overflow timers with the current MMCR0 state */
pmu_update_overflow_timers(env);
}
void helper_store_mmcr1(CPUPPCState *env, uint64_t value)
@ -152,6 +221,8 @@ void helper_store_pmc(CPUPPCState *env, uint32_t sprn, uint64_t value)
pmu_update_cycles(env);
env->spr[sprn] = value;
pmc_update_overflow_timer(env, sprn);
}
static void fire_PMC_interrupt(PowerPCCPU *cpu)