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arm: xlnx-versal: Connect usb to virt-versal 

Connect VersalUsb2 subsystem to xlnx-versal SOC, its placed
in iou of lpd domain and configure it as dual port host controller.
Add the respective guest dts nodes for "xlnx-versal-virt" machine.

Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1607023357-5096-5-git-send-email-sai.pavan.boddu@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Vikram Garhwal 2020-12-04 00:52:37 +05:30 committed by Peter Maydell
parent e29c7db19d
commit 144677d41b
3 changed files with 90 additions and 0 deletions
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55
hw/arm/xlnx-versal-virt.c
View File

@ -39,6 +39,8 @@ struct VersalVirt {
uint32_t ethernet_phy[2];
uint32_t clk_125Mhz;
uint32_t clk_25Mhz;
uint32_t usb;
uint32_t dwc;
} phandle;
struct arm_boot_info binfo;
@ -66,6 +68,8 @@ static void fdt_create(VersalVirt *s)
s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt);
s->phandle.clk_125Mhz = qemu_fdt_alloc_phandle(s->fdt);
s->phandle.usb = qemu_fdt_alloc_phandle(s->fdt);
s->phandle.dwc = qemu_fdt_alloc_phandle(s->fdt);
/* Create /chosen node for load_dtb. */
qemu_fdt_add_subnode(s->fdt, "/chosen");
@ -148,6 +152,56 @@ static void fdt_add_timer_nodes(VersalVirt *s)
compat, sizeof(compat));
}
static void fdt_add_usb_xhci_nodes(VersalVirt *s)
{
const char clocknames[] = "bus_clk\0ref_clk";
const char irq_name[] = "dwc_usb3";
const char compatVersalDWC3[] = "xlnx,versal-dwc3";
const char compatDWC3[] = "snps,dwc3";
char *name = g_strdup_printf("/usb@%" PRIx32, MM_USB2_CTRL_REGS);
qemu_fdt_add_subnode(s->fdt, name);
qemu_fdt_setprop(s->fdt, name, "compatible",
compatVersalDWC3, sizeof(compatVersalDWC3));
qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
2, MM_USB2_CTRL_REGS,
2, MM_USB2_CTRL_REGS_SIZE);
qemu_fdt_setprop(s->fdt, name, "clock-names",
clocknames, sizeof(clocknames));
qemu_fdt_setprop_cells(s->fdt, name, "clocks",
s->phandle.clk_25Mhz, s->phandle.clk_125Mhz);
qemu_fdt_setprop(s->fdt, name, "ranges", NULL, 0);
qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 2);
qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 2);
qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.usb);
g_free(name);
name = g_strdup_printf("/usb@%" PRIx32 "/dwc3@%" PRIx32,
MM_USB2_CTRL_REGS, MM_USB_0);
qemu_fdt_add_subnode(s->fdt, name);
qemu_fdt_setprop(s->fdt, name, "compatible",
compatDWC3, sizeof(compatDWC3));
qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
2, MM_USB_0, 2, MM_USB_0_SIZE);
qemu_fdt_setprop(s->fdt, name, "interrupt-names",
irq_name, sizeof(irq_name));
qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
GIC_FDT_IRQ_TYPE_SPI, VERSAL_USB0_IRQ_0,
GIC_FDT_IRQ_FLAGS_LEVEL_HI);
qemu_fdt_setprop_cell(s->fdt, name,
"snps,quirk-frame-length-adjustment", 0x20);
qemu_fdt_setprop_cells(s->fdt, name, "#stream-id-cells", 1);
qemu_fdt_setprop_string(s->fdt, name, "dr_mode", "host");
qemu_fdt_setprop_string(s->fdt, name, "phy-names", "usb3-phy");
qemu_fdt_setprop(s->fdt, name, "snps,dis_u2_susphy_quirk", NULL, 0);
qemu_fdt_setprop(s->fdt, name, "snps,dis_u3_susphy_quirk", NULL, 0);
qemu_fdt_setprop(s->fdt, name, "snps,refclk_fladj", NULL, 0);
qemu_fdt_setprop(s->fdt, name, "snps,mask_phy_reset", NULL, 0);
qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.dwc);
qemu_fdt_setprop_string(s->fdt, name, "maximum-speed", "high-speed");
g_free(name);
}
static void fdt_add_uart_nodes(VersalVirt *s)
{
uint64_t addrs[] = { MM_UART1, MM_UART0 };
@ -515,6 +569,7 @@ static void versal_virt_init(MachineState *machine)
fdt_add_gic_nodes(s);
fdt_add_timer_nodes(s);
fdt_add_zdma_nodes(s);
fdt_add_usb_xhci_nodes(s);
fdt_add_sd_nodes(s);
fdt_add_rtc_node(s);
fdt_add_cpu_nodes(s, psci_conduit);

26
hw/arm/xlnx-versal.c
View File

@ -145,6 +145,31 @@ static void versal_create_uarts(Versal *s, qemu_irq *pic)
}
}
static void versal_create_usbs(Versal *s, qemu_irq *pic)
{
DeviceState *dev;
MemoryRegion *mr;
object_initialize_child(OBJECT(s), "usb2", &s->lpd.iou.usb,
TYPE_XILINX_VERSAL_USB2);
dev = DEVICE(&s->lpd.iou.usb);
object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps),
&error_abort);
qdev_prop_set_uint32(dev, "intrs", 1);
qdev_prop_set_uint32(dev, "slots", 2);
sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
memory_region_add_subregion(&s->mr_ps, MM_USB_0, mr);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_USB0_IRQ_0]);
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
memory_region_add_subregion(&s->mr_ps, MM_USB2_CTRL_REGS, mr);
}
static void versal_create_gems(Versal *s, qemu_irq *pic)
{
int i;
@ -333,6 +358,7 @@ static void versal_realize(DeviceState *dev, Error **errp)
versal_create_apu_cpus(s);
versal_create_apu_gic(s, pic);
versal_create_uarts(s, pic);
versal_create_usbs(s, pic);
versal_create_gems(s, pic);
versal_create_admas(s, pic);
versal_create_sds(s, pic);

9
include/hw/arm/xlnx-versal.h
View File

@ -21,6 +21,7 @@
#include "hw/net/cadence_gem.h"
#include "hw/rtc/xlnx-zynqmp-rtc.h"
#include "qom/object.h"
#include "hw/usb/xlnx-usb-subsystem.h"
#define TYPE_XLNX_VERSAL "xlnx-versal"
OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
@ -59,6 +60,7 @@ struct Versal {
PL011State uart[XLNX_VERSAL_NR_UARTS];
CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];
XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS];
VersalUsb2 usb;
} iou;
} lpd;
@ -88,6 +90,7 @@ struct Versal {
#define VERSAL_UART0_IRQ_0 18
#define VERSAL_UART1_IRQ_0 19
#define VERSAL_USB0_IRQ_0 22
#define VERSAL_GEM0_IRQ_0 56
#define VERSAL_GEM0_WAKE_IRQ_0 57
#define VERSAL_GEM1_IRQ_0 58
@ -125,6 +128,12 @@ struct Versal {
#define MM_OCM 0xfffc0000U
#define MM_OCM_SIZE 0x40000
#define MM_USB2_CTRL_REGS 0xFF9D0000
#define MM_USB2_CTRL_REGS_SIZE 0x10000
#define MM_USB_0 0xFE200000
#define MM_USB_0_SIZE 0x10000
#define MM_TOP_DDR 0x0
#define MM_TOP_DDR_SIZE 0x80000000U
#define MM_TOP_DDR_2 0x800000000ULL